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sRIO SERIAL BUFFER FLOW-CONTROL DEVICE
Advanced Datasheet 80KSBR200
Device Overview
The IDT80KSBR200 is a high speed Serial Buffer (SerB) that can connect to any Serial RapidIO compliant interface. This device is built to work with any sRIO device and especially with the IDT Pre-Processing Switch (PPS), IDT70K200. The SerB performs buffering and off-loading of data as well as buffer-delay of data samples in various environments. This device primarily acts as an master in which the SerB bursts data to a programmed memory location once some criteria have been meet. This combination of storage and flexibility make it the perfect buffering solution for sRIO systems.

Programmable Target Address Packet Tally Indicator Packet Interval Timer Replace Missing Packet Optional External QDR SRAM Available

- - - - -
Up to 72Mbit external QDR SRAM QDR SRAM, 200 MHz; (18M, 36M, 72M) Internal and external memory functions as a single buffer
Seamless Integration of Internal and External Memory Single Port Buffering Status Flags for Combined Internal/External Memories
Full, Empty, Partially Empty, Partially Full
Features

Direct or polled operation of flag status bus Optional Watermark Interface - I2C Interface Port
Serial Buffer can Either Send a Flag or Transmit Data at a Specific Packet Count One I2C port for maintenance and error reporting JTAG Functionality for boundary scan and programming 1.2V Core operation with 3.3/2.5V JTAG interface 23mm x 23mm, 1.0mm ball pitch
Serial RapidIO Port Interface - sRIO

- - - - - - -
- - - -
One four-lane (4x) link, configurable to one-lane (1x) link Port Speeds selectable: 3.125 Gbps, 2.5 Gbps, or 1.25 Gbps Short haul or long haul reach for each PHY speed Support 8-bit and 16-bit deviceID Error management supports standard sRIO version 1.3 Class 1+ End Point Device
Interface - JTAG Interface High-Speed CMOS Technology Package: 484-pin Plastic Ball Grid Array
10 Gbps Throughput 18Mbit Internal Density
Block Diagram
S-Port 1
Input Deserializer S-Port 1 Command Interpreter
MUX 10
1x/4x sRIO Interface
Output Serializer
Queue 0 18 Mbits
TCK TMS TDI TDO SCL SDA MR FR
JTAG
Configuration and Flag Registers
I2 C
MUX 3
2
PHY Clk QDR Clk
Flags
32+4 bit Parallel
8
2
Flag Request Flag Clk Flag Bus Interrupt
32+4 bit Parallel
2
2
P-Port
drw01 DSC-6730
Hardwire Config
K/K
CQ CQ D
Q
A Rd Wr
1 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
2 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
Table of Contents
1.0 Functional Description
Interface Overview
9
10
2.0 Applications
PPS Data Storage Compatible External Memory
13
13 13
3.0 Protocols
SerB Packet Characteristics sRIO Specification sRIO Simplified Overview The sRIO Packet The sRIO Control Symbols Use of CRC and CRC Errors Parallel Port Interface
15
15 15 17 18 24 24 24
4.0 Data Handling
Inputting Data to the Queues Outputting Data from the Queues Use of Acknowledgements Idles Case Scenarios Water Levels and Watermarks Missing Packet Detection and Replacement Packet Tally Indicator Packet Interval Timer Protocol Translation
25
25 25 26 27 27 28 29 31 31 31
5.0 Doorbells and Interrupts
Doorbell Characteristics External Interrupt Pins
33
33 34
6.0 Device Programming
Vendor IDs Memory Map Programming and Reset
35
35 35 37
7.0 Error Management
sRIO Errors and Error Handling System Software Error Notification sRIO Errors Supported Other SerB Errors
41
41 41 42 61
8.0 Registers
sRIO Registers Configuration Registers SerB Error Counter Registers Serdes Quad Control Registers Flag and Flag Mask Registers
63
63 88 100 102 102
9.0 Reset and Initialization
Speed Select sRIO Reset Control Symbol JTAG Reset System Initialization Initialization of RIO Ports
111
111 111 111 111 112
10.0 Reference Clock
Reference Clock Electrical Specifications
113
113
11.0 Absolute Maximum Ratings
3 of 172
114
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes 12.0
Recommended Temperature and Operating Voltage AC Test Conditions I2C-Bus I2C Device Address Signaling Figures I2C DC Electrical Specifications I2C AC Electrical Specifications I2C Timing Waveforms Serial RapidIOtm AC Specifications Overview Signal Definitions Equalization Explanatory Note on XMT and RCV Specifications Transmitter Specifications Receiver Specifications
115 115
117
117 117 118 119 120 121
13.0
123
123 123 124 124 124 127
14.0 Parallel Port Electrical Characteristics
AC Electrical Characteristics
131
131
15.0 JTAG Interface
IEEE 1149.1 (JTAG) & IEEE 1149.6 (AC Extest) Compliance System Logic TAP Controller Overview Signal Definitions Test Data Register (DR) Instruction Register (IR) Usage Considerations JTAG Configuration Register Access JTAG DC Electrical Specifications JTAG AC Electrical Specifications JTAG Timing Specifications
135
135 135 135 136 139 141 142 143 144 144
16.0 Pinout & Pin Listing
Pinout Pin Listing
145
145 146
17.0 Package Specifications
Package Physical & Thermal Specifications Package Drawings
169
169 170
18.0 References & Standards 19.0 Revision History
Advanced Datasheet: Definition
172 172
172
20.0 Ordering Information
172
4 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
List of Tables
Table 1: SerB Memory Map Table 2: Port-write Packet Data Payload for Error Reporting Table 3: Physical RIO Errors Detected Table 4: Physical RIO Threshold Response Table 5: Hardware Errors for NRead Transaction Table 6: Hardware Errors for Maintenance Read/Write Request Transaction Table 7: Hardware Errors for RIO Write Class Transactions Table 8: Hardware Errors for SWrite Class Transactions Table 9: Hardware Errors for Maintenance Response Transactions Table 10: Hardware Errors for Response Transactions Table 11: Hardware Errors for Reserved FType Table 12: RIO Base Feature Address Space Table 13: Device ID CAR Table 14: Device Information CAR Table 15: Assembly ID CAR Table 16: Assembly Info CAR Table 17: Process Element Features CAR Table 18: Source Operations CAR Table 19: Destination Operations CAR Table 20: Processing Element Logical Layer Control CSR Table 21: Local Configuration Space Base Address 1 CSR Table 22: Base Device ID CSR Table 23: Host Base Device ID Lock CSR Table 24: Component Tag CSR Table 25: RIO Extended Features Address Space Table 26: 1x/4x LP-Serial Register Block Header Table 27: Port Link Time-out CSR Table 28: Port Response Time-out CSR Table 29: Port General Control CSR Table 30: Port 0 Link Maintenance Request CSR Table 31: Port 0 Link Maintenance Response CSR Table 32: Port 0 Local ackID Status CSR Table 33: Port 0 Error and Status CSR Table 34: Port 0 Control CSR Table 35: Error Management Extensions Block Header Table 36: Logical/Transport Layer Error Detect CSR Table 37: Logical/Transport Layer Error Enable CSR Table 38: Logical/Transport Layer Address Capture CSR Table 39: Logical/Transport Layer Device ID Capture CSR Table 40: Logical/Transport Layer Control Capture CSR Table 41: Port-write Target Device ID CSR Table 42: Port 0 Error Detect CSR Table 43: Port 0 Error Rate Enable CSR Table 44: Port 0 Attribute Capture CSR Table 45: Port 0 Packet/Control Symbol Capture 0 CSR Table 46: Port 0 Packet/Control Symbol Capture 1 CSR Table 47: Port 0 Packet/Control Symbol Capture 2 CSR Table 48: Port 0 Packet/Control Symbol Capture 3 CSR Table 49: Port 0 Error Rate CSR Table 50: Port 0 Error Rate Threshold CSR Table 51: Reset and Command Register Table 52: Serial Port Configuration Register Table 53: Parallel Port Configuration Register Table 54: Memory Allocation Register 5 of 172 35 42 42 44 45 47 51 53 54 57 60 64 64 65 65 65 66 67 67 68 69 69 70 70 71 72 72 72 73 73 74 74 75 77 78 78 79 81 81 82 82 83 83 85 85 86 86 86 87 88 89 90 90 90 March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet* Table 55: Lost Packet Replacement Register Table 56: Source and Destination ID Register Table 57: PAE / PAF Register Table 58: Watermark Register Table 59: Waterlevel Register Table 60: Space Available Register Table 61: MBIST Control Register Table 62: QBIST Control Register Table 63: JTAG Device ID Register Table 64: Case Scenario Packet Header Register Table 65: Case Scenario Start Address Register Table 66: Case Scenario Next Address Register Table 67: Case Scenario Stop Address Register Table 68: Case Scenario Frame Register Table 69: Missing Packet Start Address Register Table 70: Missing Packet Current Address Register Table 71: Missing Packet Address Increment Register Table 72: Missing Packet Stop Address Register Table 73: Data Packet Interval Timer Register Table 74: Doorbell Packet Interval Timer Register Table 75: Missing Packet Size Register Table 76: Missing Packet Address Logging Register Table 77: Missing Packet Address Logging Register for TI DSP Table 78: S-Port Data Packet Received Counter Table 79: S-Port Data Packet Transmitted Counter Table 80: S-Port Priority Packet Received Counter Table 81: S-Port Priority Packet Transmitted Counter Table 82: S-Port Packet Received Counter Table 83: S-Port Packet Transmitted Counter Table 84: SERDES Quad Control Register Table 85: Flag and Flag Mask Register Table 86: S-Port Link Status Register Table 87: Device Configuration Error Register Table 88: sRIO DMA Status Register Table 89: Missing Packet Flag Register Table 90: FIFO Queue Empty Flag Register Table 91: FIFO Queue Full Flag Register Table 92: DSP Interrupt Flag Register Table 93: Tally Doorbell Flag Register Table 94: Missing Packet Programmable Flag Register Table 95: Port Speed Selection Pin Values Table 96: Input Reference Clock Jitter Specification Table 97: Absolute Maximum Ratings Table 98: Recommended Temperature and Operating Voltage Table 99: AC Test Conditions (Vdd3 = 3.3V / 2.5V); JTAG, I2C, RST Table 100: Typical Power Figures Table 101: I2C Static Address Selection Pin Configuration Table 102: P-Port AC Electrical Characteristics Table 103: JTAG Pin Description Table 104: Instructions Supported by 80KSBR200's JTAG Boundary Scan Table 105: System Controller Device ID Register Table 106: System Controller Device ID Instruction Format Table 107: Data Stream for JTAG Configuration Register Access Mode Table 108: Pin Listings 91 91 92 92 92 92 93 93 94 95 95 96 96 97 97 98 98 98 99 99 99 99 100 100 100 101 101 101 102 102 103 104 104 105 106 106 107 108 109 109 111 113 114 115 115 116 117 132 135 139 140 141 142 146
Notes
6 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
List of Figures
Figure 1: Diagram of SerB Interfaces Figure 2: PPS Data Storage Figure 3: Generic sRIO Request Packet Figure 4: sRIO Physical Layer Header Figure 5: Transaction Types (8 or 16) Figure 6: Transaction ID Range for sRIO Packet Generating Entities Figure 7: sRIO Maintenance Request Packet (Type 8) Figure 8: sRIO Maintenance Response Packet (Type 8) Figure 9: Typical sRIO Packet showing location of Source and Destination IDs Figure 10: sRIO Doorbell Packet Figure 11: Reset Timeline Figure 12: REF_CLK Representative Circuit Figure 13: AC Output Test Load (JTAG) Figure 14: AC Output Test Load (I2C) Figure 15: sRIO Lanes Test Load Figure 16: Write Protocol with 10-bit Slave Address (ADS = 1) Figure 17: Read Protocol with 10-bit Slave Address (ADS = 1) Figure 18: Write Protocol with 7-bit Slave Address (ADS = 0) Figure 19: Read Protocol with 7-bit Slave Address (ADS = 0) Figure 20: I2C SDA & SCL DC Electrical Specifications (VDD3 = 3.3V) Figure 21: I2C SDA & SCL DC Electrical Specifications (VDD3 = 2.5V) Figure 22: Specification of the SDA & SCL bus lines for F/S-mode I2C-bus Device Figure 23: I2C Timing Waveform Figure 24: Differential Peak-Peak Voltage of Transmitter or Receiver Figure 25: Short Run Transmitter AC Timing Specifications - 1.25 GBaud Figure 26: Short Run Transmitter AC Timing Specifications - 2.5 GBaud Figure 27: Short Run Transmitter AC Timing Specifications - 3.125 GBaud Figure 28: Long Run Transmitter AC Timing Specifications - 1.25 GBaud Figure 29: Long Run Transmitter AC Timing Specifications - 2.5 GBaud Figure 30: Long Run Transmitter AC Timing Specifications - 3.125 GBaud Figure 31: Transmitter Output Compliance Mask Figure 32: Transmitter Differential Output Eye Diagram Parameters Figure 33: Receiver AC Timing Specifications - 1.25 GBaud Figure 34: Receiver AC Timing Specifications - 2.5 GBaud Figure 35: Receiver AC Timing Specifications - 3.125 GBaud Figure 36: Single Frequency Sinusodial Jitter Limits Figure 37: Receiver Input Compliance Mask Figure 38: Receiver Input Compliance Mask Parameters Exclusive of Sinusodial Jitter Figure 39: P-Port Signals Connected to a QDRII SRAM Figure 40: Timing Waveform of Combined Read and Write Cycles Figure 41: Diagram of the JTAG Logic Figure 42: State Diagram of the 80KSBR200's TAP Controller Figure 43: Diagram of Observe-only Input Cell Figure 44: Diagram of Output Cell Figure 45: Diagram of Output Enable Cell Figure 46: Diagram of Bi-directional Cell Figure 47: Implementation of Write during Configuration Register Access Figure 48: Implementation of Read during Configuration Register Access Figure 49: JTAG DC Electrical Specifications (VDD3 = 3.3V) Figure 50: JTAG DC Electrical Specifications (VDD3 = 2.5V) Figure 51: JTAG AC Electrical Specifications Figure 52: JTAG Timing Specifications 7 of 172 10 13 18 19 19 22 23 23 27 33 111 113 115 116 116 118 118 119 119 119 120 120 121 123 124 125 125 125 126 126 127 127 128 128 129 129 130 130 131 133 135 136 137 137 138 138 142 143 143 143 144 144 March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet* Figure 53: 80KSBR200 Pinout Figure 54: SerB Package Drawing (1 of 2) Figure 54: SerB Package Drawing (2 of 2) 145 170 170
Notes
8 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
1.0 Functional Description
The IDT80KSBR200 is a Serial RapidIOTM sequential buffer (SerB) flow-control device consisting of up to 18Mbits of on-chip memory with expansion of one QDR SRAM externally bringing the total buffering capacity to 90Mbits of storage. This device is built to work with any sRIO device and especially with the IDT Pre-Processing Switch (PPS) number IDT70K200. In this configuration, the main application is working in conjunction with the PPS. In applications were multiple DPSs are used with the PPS, the SerB can function as an over-flow port to handle traffic that is block on any given port or, as a delay buffer to store data and present it at a later time. This is important in DPS applications were time samples are compared with the previous sample such as Cellular Base Stations. Please refer to the application note "Serial Buffer and Pre-Processing Switch". The SerB fully complies to the sRIO specification version 1.3 and is implemented to a class 1+ end-point device. This device operates as a master. In the sRIO environment, a master is defined as a device that originates data transfers, either to or from that device. A slave is one that responds to commands from other devices to move data. As a master, the SerB can receive data and at a pre-programmed water level (number of packets), the device will form and transmit either packets or status (e.g., doorbells) to a programmed location. The SerB performs buffering and off-loading of data as well as buffer-delay of data samples in various environments. This device can act as a master in which the SerB writes data to a programmed location once the criteria have been meet. This combination of storage and flexibility make it the perfect buffering solution for sRIO systems. For applications requiring larger buffers, an additional 72Mbits of QDR SRAM can be attached via the Parallel Port. The two memories are seamlessly connected by the Serial Buffer to form a large, 90 Mbit buffer memory. The QDR SRAM interface runs at speeds of only 156.25MHz allowing lower cost memories to be used as well as easier board layout. Data rates still support up to 10Gbits/s (OC-192) thoughput in the device to maintain full sRIO four-lane compliance. The device provides Full flag and Empty flag status for the queue for write and read operations respectively. Also a Programmable Almost Full and Almost Empty flag for the queue is provided. A JTAG test port is provided running at 3.3V, device has a fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. The SerB can also be programmed via the JTAG port. There is also an I2C processor port for programming and retrieving information from the configuration registers. The device is configured into a single queue comprising the full internal memory and potentially the external memory if attached. The device treats the full amount of memory, wether internal or a combination of internal and external, as a single memory block. Status flags from that queue, either referring to the writes (full flags) or the reads (empty flags) to or from that queue represent the total amount of memory. Flags can be read from the serial port or from the I2C or JTAG port. Proactive flags can be configured to send a doorbell and/or change the interrupt pin once a flag is set. Partial full and empty flags can be programmed to provide reaction time for writes and reads respectively. Flags associated with reaching water marks are available in addition to the full and empty flags. Further information regarding this device and follow-on devices with added functionality are available from IDT.
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
1.1 Interface Overview
sRIO 4 Tx lanes 1.25, 2.5 or 3.125Gbps
P-Port Clock (4-pins)
sRIO 4 Rx lanes 1.25, 2.5 or 3.125Gbps
. . . . . .
P-Port Address (23 pins)
JTAG Interface (5 pins)
IDT80KSBR200 Serial Buffer (SerB)
P-Port Rd/Wr Ctrl P-Port D Bus (36 pins) P-Port Q Bus (36 pins)
I C Interface 400Khz F/S (13-pins)
2
. . .
IRQ Output (2 pins)
Master Reset REF_Clock (2 pins) R_Ext (External Resistance)
Figure 1 Diagram of SerB Interfaces
1.1.1 sRIO Port The sRIO interface is the main communication port on the chip. This port is compliant with the serial RapidIOTM v. 1.3 specifications. Please refer to the serial RapidIOTM specifications for full detail. There are 4 uni-directional differential links for a total of 8 pins. Each can run at 1.25, 2.5, or 3.125Gbps programmable. Both sRIO data (sample) and maintenance packets are transmitted and received on these links. 1.1.2 Parallel Port P-Port interface is used as a memory expansion port. As a memory expansion port, one of the designated QDR SRAM devices can be connected. If P-Port is connected to one of the designated SRAM devices, it will maintain the clocking and full interconnection to drive the SRAM device. 1.1.3 I2C Bus This interface may be used as an alternative to the standard sRIO or JTAG ports to program the chip and to check the status of registers - including the error reporting registers. It is fully compliant with the I2C specification, It has 13 pins and supports both Fast- and Slow-mode buses [1]. Refer to the "I2C" chapter for full detail. 1.1.4 JTAG TAP Port This TAP interface is IEEE1149.1 (JTAG) and 1149.6 (AC Extest) compliant [10, 11]. It may also be used as an alternative to the standard sRIO or I2C ports to program the chip and to check the status of registers - including the error reporting registers. It has 5 pins. Refer to the JTAG chapter for full detail.
10 of 172
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
1.1.5 Interrupt (IRQ)
An interrupt output is provided in support of Error Management functionality. This output may be used to flag a host processor in the event of error conditions within the device. Refer to the Error Management section for full detail. 1.1.6 Reset A single Reset pin is used for full reset of the SerB, including setting all registers to power-up defaults. Refer to the Reset & Initialization section for full detail. 1.1.7 Clock The single system clock (REF_CLK+ / -) is a 156.25 MHz differential clock input. Refer to the Clock section for full detail. 1.1.8 R-Ext (Rextn & Rextp) These pins are used to establish the drive bias on the SERDES output. An external bias resistor is required. The two pins must be connected to one another with a 12k Ohm resistor. This provides CML driver stability across process and temperature. 1.1.9 SPD[1:0] Speed Select Pins. These pins define the sRIO port speed at RESET. The RESET setting may be overridden by subsequent programming of the Serial Port Configuration Register. SPD[1:0] = {00 = 1.25G, 01 = 2.5G, 10 = 3.125G, 11 = RESERVED}. These pins must remain STATICALLY BIASED after power-up.
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
12 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
2.0 Application
2.1 PPS Data Storage
The SerB's primary application is for a Basestations using the IDT's Pre-Processing Switch (PPS). The SerB will be a storage device, holding large amounts of data passed to it by the PPS and with all of its internal memory allocated to queue 0. In this application, the S-Port on the SerB will connect to one of the 4x ports of the PPS. The PPS will pass approximately 10ms of data to the SerB at which time the SerB will start to pass it back to the PPS as a multicast. It is expected that the data flow will remain constant with 10ms (or other designated quantity) worth of data always in storage. The Basestation uses the data for decryption purposes. The following are items of note concerning the PPS application: The SerB has the ability to act as a simple master. - The SerB's application with the PPS will be to broadcast data. It must be a master to perform a broadcast, even if the data is requested. - The SerB has the ability to initiate writes. Mainly to prevent overflow and to perform broadcasts when waterlevel is reached (timed event). This avoids requiring the DSP to increase congestion by requesting data and controlling the SerB. The SerB will typically perform SWRITEs. - The target address(s) generated by the SerB is programmable. - The packets are stored in the format they come in and are rebroadcast with simple changes to the headers The DSPs have the ability to read the SerB registers through the PPS. - The DSP may send a maintenance read/write packets to the SerB requesting register information.
Input Serializer Command Interpreter
sRIO
High Speed Serial Lines
Output Serializer Command Generator
Queue 0
Data
Address
CNTL
Figure 2 PPS Data Storage
2.2 Compatible External Memories
The P-Port, as a FIFO controller shall connect to an external memory device. There are two designated memory devices, which may be connected to the SerB. These are: QDRII-B4 SRAM with 36-bit bus in 36M size QDRII-B4 SRAM with 36-bit bus in 72M size Only one memory may be connected to the P-Port at a time. Initial release of the SerB will only support 72M density and support of other devices listed above to follow with subsequent release. Expansion is available only through increased memory size. 2.2.1 Memory Default Configurations: The memory default configuration on power up or hard reset is as follows:
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
QDR2 SRAM
High Speed Serial Lines
QDRII Memory Controller
External Memory Interface
Data
IDT 80KSBR200
Advanced Datasheet*

Notes
No external memory is allocated, regardless of whether external memory is present. All SRAM is allocated to queue 0 P-Port outputs default to valid states to prevent possible damage to external devices, unless P-Port is physically disabled by the external pin.
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
3.0 Protocol
The SerB is a packet-handling device. The SerB may be configured to require all packets to be acknowledged, and hold all packets available for retransmission until acknowledgement is received. Incoming corrupted packets are dropped and issues a retransmission request. The negotiation for acknowledgement, retransmission and dropping packets is handled at the local interface level, without intervention of higher-level authorities. The SerB does not forward any packet until it is fully received, verified, and acknowledged (if configured to verify).
3.1 SerB Packet Characteristics
3.1.1 Maximum Packet Size The sRIO specification requires a maximum packet size of 256 bytes plus overhead. The SerB fully complies to this specification. 3.1.2 Interface Packet Buffer Size The sRIO specification has defined buffer sizes for the transmit and receive buffers. Included in the buffer specification is the requirement to transmit higher priority packets first. Upon transmission failure, and retransmission, the retransmission may be held up and a higher priority packet interjected if one arrives. 3.1.3 Multicast Packets The SerB has no special multicast capabilities. To perform a multicast, the case scenario should be set up to perform an SWRITE function. The destination ID for the case scenario should be set to a multicast address elsewhere in the system. The SerB shall perform a multicast by sending the SWRITE to the user designated multicast address, along with the data. Waterlevel multicast in the PPS application is done the same way. When the waterlevel event is triggered, the SerB issues an SWRITE multicast packet to the PPS multicast address. The SWRITE command is generated by the case scenario.
3.2 sRIO Specification
The SerB serial interface is a standard 1x/4x serial port with sRIO capabilities. In the PPS application, the sRIO port act primarily as an sRIO end-point, but will work as a bus master to perform multicast operations. All the RIO TWG documents can be found on the RapidIO Members website: http://www.rapidio.org/apps/org/workgroup/twg/documents.php The following documents are the final version 1.2 specifications, which can be found under the Members Library section, version 1.3 of the specifications will replace these section files when they are approved by the Steering Committee: RapidIO_Spec.pdf gsmlspec.pdf serial.book.pdf inter-op.pdf errspec.pdf errata1.pdf fcspec.pdf system_bringup_spec.pdf The version 1.3 files are currently: IO_logical.pdf msg_logical.pdf cmn_trnspt.pdf parallel_phy.pdf Part I through part IV of the spec., version 1.2 Part V of the spec., version 1.2 Part VI of the spec., version 1.2 Part VII of the spec., version 1.2 Part VIII of the spec., version 1.2 Errata 1 to version 1.2 of the spec. Part IX of the spec., version 1.0 Annex I of the spec.
Part 1: Input/Output Logical Specification Part 2: Message Passing Logical Specification Part 3: Common Transport Specification Part 4: Physical Layer 8/16 LP-LVDS Specification
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gsmlspec.pdf serial_book.pdf inter-op.pdf errspec.pdf fcspec.pdf encapspec.pdf mcspec.pdf sbtg.pdf
Part 5: Globally Shared Memory Specification Part 6: 1x/4x LP-Serial Physical Layer Specification Part 7: System and Device Inter-operability Spec Part 8: Error Management Extensions Specification Part 9: Flow Control Logical layer Specification Part 10: Data Streaming logical Specification Part 11: Multicast Extensions Specification Annex 1: Software/System Bring Up Specification
There is a checklist for compliance to version 1.3 of the RIO specification, which will be used to insure proper RIO operation. 3.2.1 RapidIO Spec. Version 1.3 In compliance with the sRIO specification, the port has the ability to connect directly to a 1x/4x sRIO port on the PPS device, or connect to any other sRIO compliant 1x/4x port. This includes the standard lane fail functions where a failure of any lane on a 4x port will force the device into a 1x operation on lane 0 or lane 2. The SerB has no requirement to perform with more than a single 1x port. Restated, S-Port shall be either a 4x port or a 1x port as designated by the configuration or fail mode, but shall never be four 1x ports operating simultaneously. The RIO specification is a universal specification and all sections do not fully apply to the SerB. Each of the parts of the specification will be listed individually below along with the compliance level for the SerB. Some of the documents are not complete and published. Some are working group showings. Each chapter is discussed in a separate section below. Part 1: Input/Output Logical Specification The SerB device shall abide by this spec. Part 2: Message Passing Logical Specification The SerB device shall abide by this spec. Part 3: Common Transport Specification The SerB device shall abide by this spec. Part 4: Physical Layer 8/16 LP-LVDS Specification The SerB device does not support this spec. Part 5: Globally Shared Memory Logical Specification The SerB device does not support this spec. Part 6: Physical Layer 1x/4x LP-Serial Specification The SerB shall abide by this spec. Part 7: System and Device Inter-operability Specification The SerB device shall comply with the Generic Class Requirements (class 1+). Part 8: Error Management Extensions Specification The SerB device shall comply with this spec. Part 9: Flow Control Logical Layer Specification The SerB devices does not support this spec. Part 10: Data Streaming Logical Specification The PPS device does not support this spec. Part 11: Multicast Extensions Specification SerB device shall abide by this spec (do nothing). A multicast for SerB is a simple write to an address.
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Annex I: Software/System Bring Up Specification Already comply. Approved Showings The following documents are approved showings in the TWG. Each of them will be discussed in detail. 04-11-00031.001 Change to the spec of the Serial RapidIO Receiver Sinusoidal Jitter Tolerance Mask. IDT SerDes is tuned to this spec. 3.2.2 Summation of RIO registers The SerB shall include all registers required by the RIO spec for configuration. 3.2.3 sRIO Priorities sRIO has two forms of priority. The first is the Standard sRIO priority. The second is the Virtual Channel form of sRIO. There is a bit set in the data stream where VC = 0 designates standard sRIO priorities, while VC = 1 designates virtual channels. The SerB shall not use virtual channels, but pass any virtual channel data as if it were sent with standard priority. Standard sRIO has four discrete levels of priority (two bits). Added to the priority is the CRF (Critical Request Flow) bit which is a priority distinguishing bit within a priority (LSB), bringing the total number of priority bits to three. High priority packets are always sent before lower priority packets. Low priority packets do not enter the data stream until the high priority packets are exhausted. The SerB ignores the CRF bit. In virtual channel prioritization, there are three bits that designate the virtual channel. These replace the sRIO two bit priority plus CRF bit. With virtual channels, each channel is allocated a percentage of the total bandwidth. In this application, all channels are allocated some bandwidth regardless of their priority, preventing high priority packets from stealing the entire bandwidth. The SerB shall not support Virtual Channels, but instead will always transmit higher priority packets first. The sRIO user may transmit data on any priority with little regard to volume of data. For instance if there operating at close to full bandwidth with critical data, but would like to support additional service on an "as bandwidth available" basis, he may be running with most traffic on the higher priorities and limited capacity on low priorities. The response packet sent in most applications is intended to be sent at one priority level higher than the received packet, which would limit the usage of the top priority to response packets, but it is not guaranteed that the user would not use the highest priority for other data.
3.3 sRIO Simplified Overview
The operation of the sRIO bus is contained in the sRIO specification. The following comments are provided to provide a superficial understanding of the initialization of the interface, without researching the specifications. 3.3.1 sRIO Sync The sRIO sync is accomplished by the transmitter sending continuous /K28.5/ codes (commas) on each lane until sync is accomplished. The state machine is shown on page VI-58 of the Physical Layer x1/x4 LP-Serial Specification for RapidIO. The sync is tolerant of occasional /INVALID/ code groups as shown in the state machine and will increase or decrease level of sync, based upon the error level of the interface. Upon completion of sync, each serial lane should be able to successfully transmit and receive 8B/10B codes. 3.3.2 sRIO Alignment After sync, the lane alignment must be completed. This is accomplished by sending continuous /A/s on all lanes. The / A/s are counted until lane alignment is accomplished. The state machine for the "A" counters is shown on page VI-60 of the LP-Serial Specification for RapidIO. The state machine is tolerant of an occasional /INVALID/ code group, and will increase or decrease the state of alignment (NOT_ALIGNED to ALIGNED_3) based upon the successful transfer of /A/'s on the lanes. A fully successful alignment would enable the 4x mode of sRIO. If links are broken and/or alignment is not possible, the interface will be required to operate with a single link (lane 0 or 2).
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3.3.3 sRIO Mode Initialization Once sync and alignment is accomplished, the sRIO controlling device will search for the SerB. The steps of the search include SILENT, SEEK, and then DISCOVERY. Once DISCOVERY is complete, the mode will be set to 4X_MODE (optimum performance), 1X_MODE_LANE0, or 1X_MODE_LANE2, depending upon the success of establishing the link. The state machine for the MODE is shown on page VI-64 of the LP-Serial Specification for RapidIO. 3.3.4 sRIO Control Symbols sRIO requires the transmission of control symbols providing link status every 819.2ns or less whenever the link is otherwise idle. The control symbols are described in section 5.2 of the LP-Serial Specification for RapidIO. These include delimiters /K28.3/ if a packet delimiter is included or /K28.0/ if there is no packet delimiter. 3.3.5 sRIO End-to-End Retransmissions As an sRIO bus endpoint, the SerB supports end-to-end sRIO retransmissions. This is required for the SerB to meet the sRIO compliance testing as an endpoint. When S-Port is acting as an sRIO slave, the SerB fully acknowledges all linkto-link transactions and end-to-end transactions per the sRIO specification. As an sRIO bus master, as would be the case with a waterlevel or doorbell master, the SerB has limited capabilities. At the link level, the SerB has the ability to receive acknowledgement of all transactions at the link level and perform retransmissions of any packets for which a retransmission has been requested. The SerB does not have the ability to support end-to-end retransmissions as a bus master. When a packet is sent out from the SerB as a bus master, an end-to-end response packet should be received in due time. The packet will be handled as follows: If the response is an acknowledgement -- the response will be ignored. If the response is a retransmission request - a flag will be set and the packet otherwise ignored. No retransmission will be attempted. If there is no response - the SerB will not realize there was no response, because it was not looking for one. 3.3.6 The SerB as an sRIO System Host The SerB has no ability to act as a host in an sRIO system. The SerB does have the ability to act as a bus master on occasion and will take control of the bus to accomplish the transmission of selected data items or perform selected functions. The SerB does not have the ability to control a system or fully interact and interpret the actions of other devices in the system. Bus mastering is limited to the transmission of the designated data.
3.4 The sRIO Packet
sRIO has a defined packet structure for each type of packet. The sRIO specification should be referenced for a complete description of sRIO packets and their architecture. Packet aspects that are significant in the SerB are described here for clarity, but the sRIO specification overrides in the event of a discrepancy.
Figure 3 Generic sRIO Request Packet
Looking at Figure 3, the sRIO packet contains the following items: Physical Layer Defined header, shown in Figure 4. The transaction type, TT, that defines 8 or 16 bit device ID fields, shown in Figure 5.
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The Ftype, which defines the type of packet being sent. The types are shown in section 3.4.4. The Target Address, a.k.a Destination ID. This will be 8 bits or 16 bits, depending upon the state of TT. The Source Address, a.k.a Source ID. This will be 8 bits or 16 bits, depending upon the state of TT. The Transaction, which is dependent upon the packet Ftype. The supported transactions are described individually.
3.4.1 sRIO Physical Layer Header The sRIO physical layer header is shown in Figure 14. The various fields are defined in the sRIO Physical Layer 1x/4x specification. The sRIO priority is the priority of the packet during transmission. The contents of the physical layer do not go beyond the interface, except the packet priority (Pri) may be dictated for any transmitted packet. In the SerB, there are two methods for setting the priority. If a transmitted packet is a response to a received packet, the sRIO response priority will be one priority level higher than the priority of the request packet, up to the maximum priority. If the transmitted packet is being initiated by the SerB, the priority of the packet will be dictated by the SerB. In most cases, the priority will be dictated by the "Case Scenario".
ACKID
5
Rsrv = 00 2
CR F 1
Pri o 2
Figure 4 sRIO Physical Layer Header
3.4.2 sRIO Physical Layer CRC CRC-16 accompanies all sRIO packets and is defined in the sRIO Physical Layer 1x/4x specification. The location of CRC within the packet is shown in Figure 3. 3.4.3 sRIO Transport Layer Header (8/16 bit Device IDs) During sRIO "bring up", the SerB shall support both 8 and 16 bit device ID fields. Once configured as either 8 or 16 bit, the SerB does not support the other type and will drop packets once configured. Considering that the only packet type supported is the type configured, the TT bits within the packet are not useful. The SerB insures that the proper TT bits are included in every packet sent. Incoming packet TT bits are a "don't care". Within the sRIO packet, the TT (transaction type) is used to identify the size of the fields as shown in Figure 5.
TT 00 01 10 11 Definition 8-Bit Device ID Fields 16-Bit Device ID Fields Reserved Reserved
Figure 5 Transaction Types (8 or 16)
The source and destination IDs in the sRIO packet will be either 8 or 16 bit as configured. Every sRIO packet that the SerB generates contains a Target ID that has been generated from one of following ways: The packet is in response to a request. The Target ID is the source ID of the requestor. The packet is generated by the SerB through a "case scenario". The Target ID is included in the case scenario. Any packet that is generated by a case scenario will use the Source ID of the queue to send the packet. Any flag associated with a queue will use the Source ID of the queue to send the doorbell.
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Any packet that is generated by the SerB that is unrelated to a particular queue (such as a link error) will use the device ID of the SerB as the source ID.
3.4.4 sRIO Request Packet Types (Ftype 0 - 11) Within the sRIO specification, 16 packet types may be formed. Packet types "Type 0" through "Type 11" are Request packet types. Packet types, "Type 12" through "Type 15" are Response packet types. Many of the packet types are reserved. The SerB has limited sRIO functionality, but should be able to imitate any type of command. The SerB initiates commands through the Case Scenario. Case Scenarios have the ability to initiate any type of command by simply entering the correct Ftype and the rest of the sRIO header as desired. The required data may be appended as needed. The SerB fully supports only selected sRIO commands. The user needs to be aware of the limited SerB functionality, but may be able to pass commands outside the SerB limits if the usage and expectation of the commands fits within the limits of SerB capabilities. Following are the sRIO commands SerB is capable of supporting: SWRITE (type 6) CAR/CSR (type 8) DOORBELLS (type 10) MESSAGES (type 11) (no defined message) Following are the sRIO commands supported in next phase of SerB: NREAD (type 2) NWRITE (type 5) NWRITE_R (type 5) The packet types are described in the RapidIO Interconnect Specification, Part 1: Input/Output Logical Specification in chapter 4. The following is a list of the packet types and the level of support the lite protocols shall offer. Type 0 Packet Format (Implementation Defined) Type 0 packets shall not be used on the SerB. Type 1 Packet Format (Reserved) Type 1 packets are not defined in the sRIO spec and shall not be used in the SerB. If received, they are simply passed unaltered at the logical level. Type 2 Packet Format (Request Class) Type 2 packets are described in section 4.1.5 of the sRIO spec. Type 2 is used for NREAD and ATOMIC in standard sRIO. The SerB does not support neither NREAD nor ATOMIC packet format. Type 3-4 Packet Format (Reserved) Type 3 and Type 4 packets are not defined in the sRIO spec and shall not be used in the SerB. If received, on the sRIO port with an SerB destination ID, an error message shall be sent. When a case scenario is loaded with type 3 or 4, the type shall be passed along with any data. No further interpretation should be needed. Type 5 Packet Format (Write Class) Type 5 packets are described in section 4.1.7 of the sRIO spec. Type 5 is used for NWRITE, NWRITE_R, and ATOMIC in standard sRIO. As with Type 2 packets, the priority must be identified so it can be passed. Type 6 Packet Format (Streaming-Write Class) Type 6 packets are described in section 4.1.8 of the sRIO spec. Type 6 has only one function (SWRITE), which is limited in scope with no response needed. Therefore, the entire SWRITE packet must be passed unaltered, except for the addition of a priority designation. The PPSc generates SWRITE packets, so the primary packet the SerB will see in PPS applications is SWRITE. The SerB must accept SWRITE packets as they are received, because the PPS has no backpressure mechanism and a delay in packet acceptance will mean packet loss.
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Type 7 Packet Format (Reserved) Type 7 packets are not defined in the sRIO spec and shall not be used in the SerB. If received, on the sRIO port with an SerB destination ID, an error message shall be sent. When a case scenario is loaded with type 7, the type shall be passed along with any data. No further interpretation should be needed. Type 8 Packet Format (Maintenance Class) Type 8 packets are described in section 4.1.10 of the sRIO Input/Output Logical Specification. These packets are the CARs and CSRs necessary for programming and reading the status/capability of the SerB. The SerB must fully support type 8 packets. Type 9 Packet Format (Reserved) Type 9 packets are not defined in the sRIO spec and shall not be used in the SerB. If received, on the sRIO port with an SerB destination ID, an error message shall be sent. When a case scenario is loaded with type 9, the type shall be passed along with any data. No further interpretation should be needed. Type 10 Packet Format (Doorbells) Doorbells are not defined in the sRIO, Part 1, "Input/Output Logical Specification", but are listed as "reserved" in section 4.1.11 of that spec. The Type 10 packets are defined in the Part 2, "Message Passing Logical Specification". The SerB shall issue doorbells as defined in section below. Type 11 Packet Format (Messages) There is no use identified for type 11 packets. These packets normally carry non-doorbell messages. These packets are also considered "reserved" in the "Input/Output Logical Specification", but are defined in the "Message Passing Logical Specification". 3.4.5 sRIO Response Packet Types (Ftype 12 - 15) Within the sRIO specification, packet types, "Type 12" through "Type 15" are Response packet types. Of the response type packets, all are reserved except packet type 13, which will be used for all response packets. If a response packet is received with a type other than Ftype 13, the packet shall be ignored and an error flagged. Type 13 Packet Format (Response) Ftype 13 packets are defined in the sRIO Part 1, "Input/Output Logical Specification" in section 4.2.3. The SerB fully supports Ftype 13 packets. 3.4.6 sRIO Transaction IDs Every sRIO transaction must have an ID that cannot repeat itself within a designated time. That designated time is the time that a packet may remain alive, including all blockages, retransmissions and acknowledgements. In the case of the SerB, retransmission capabilities beyond the link level are not supported, and therefore the transaction ID is not used. Regardless, the SerB must handle incoming transaction IDs and generate outgoing transaction IDs. The SerB will attempt to categorize outgoing transaction IDs. Within the SerB there are multiple sources of packets, where a queue may be generating packets, plus the device itself may generate packets. In some cases, one part of the device may not know what other parts are doing. Source ID, Destination ID, and Transaction ID all are used to identify a unique packet. In addition, response packets are identified as a "response". Using all of these identifying markers guarantees that the SerB is not capable of generating a transaction ID that would interfere with those generated by another entity. The following items describe the use of transaction IDs within the SerB. Incoming transaction IDs will be returned with any response packets. This includes any response messages, responses to NWRITE_R and other packets that require responses. Every transaction generating portion of the SerB will have it's own unique block of transaction IDs to loop on. The transaction ID includes the source ID of the transaction, so we will not be interfering with other devices in the system generating transaction IDs. There will be 32 transaction IDs allocated to every sRIO packet generating entity within the SerB. The doorbells will be allowed more, since there may be more active at a time.
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The transaction IDs are allocated per Figure 6.
ID Range 31-0 127-32 159-128 255-160 sRIO Packet Generating Entity Queue 0 Output Reserved for future use Device ID of the SerB Doorbells and reserved
Figure 6 Transaction ID Range for sRIO Packet Generating Entities
Source ID, Destination ID, and Transaction ID all are used to identify a unique packet. If this includes the transaction type or some additional ID, the problems of multiple identical transaction types would be solved. Response packets are identified as response packets, which identify the originator of the request, the source ID of the responder and the transaction ID. Combining these identifies a unique packet despite the possibility of otherwise conflicting transaction IDs. 3.4.7 sRIO Packet Blockage and Priorities The SerB is not a switch and should not be involved in blocking packets. Despite this, the SerB may be unable to transmit packets or packets may be blocked by downstream devices, requiring the SerB to hold and retransmit packets. When connected to the PPS, the SerB should not be reordering packets based upon priority, because packets are issued based upon time in the buffer and not priority. When the SerB is used in non-PPS applications, it may be necessary to transmit packets based upon priority. Blocked packets would be held and transmitted after subsequently received higher priority packets have been transmitted. In this situation, blockage may develop if the inflow to the SerB exceeds or equals the outflow. Typically higher priority packets would be initiated for command and symbol passing. 3.4.8 The sRIO Write Packet, Type 5, Special Considerations The SerB may receive and issue both type 5, NWRITE and NWRITE_R packets. The SerB has no ability to issue or receive any of the three ATOMIC packets. The wrsize accompanying the data will be stored as part of the packet header in the SerB to allow correct identification of the packet length for subsequent transmission of the packet as the packet leaves the SerB. sRIO Type 5 packets assume the recipient device is addressable as a side address memory. The SerB is a FIFO and will store the data seqentially and transmit data sequentially, regardless of the address accompanying the data. The address will be stored as part of the packet header in the SerB, and may be used when the packet is again transmitted. Despite not using the addresses for data storage, the addresses are used in some applications to detect missing packets. 3.4.9 The sRIO Maintenance Packet, Type 8, Special Considerations The sRIO Maintenance Packet is a Type 8 packet and is used for programming and/or reading the CARs and CSRs. In addition, the Port-write maintenance packet may be generated as an error response as defined by the sRIO Error Management Specification. The sRIO Maintenance Packet allows in-band control of the SerB configuration. The RIO specifications define a number of registers for end-point devices, which is described in the Register section. sRIO maintenance packets are Type 8 packets and have the ftype field set to 1000b. These packets are described in section 4.1.10 of the sRIO input/Output Logical spec. In addition, information on the tt and hop count can be found in section 1.3 of the Common Transport Specification. An example of the structure of a type 8 packet is shown in Figure 7. The configuration registers are all 32 bits or less, and all packets will carry 32 bits regardless of whether all 32 bits are needed.
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AckID transaction
rsvd
CRF
prio
tt srcTID
fType
Target ID Hop Count
Source ID config_offset Payload CRC
rdsize/wrsize config_offset Payload
wdptr
rsrv
Figure 7 sRIO Maintenance Request Packet (Type 8)

AckID = Transaction ID for link acknowledgements CRF = Critical Request Flow, not used in SerB prio = Packet priority tt = Transaction type, 00 = 8 bits, 01 = 16 bits fType = 1000, for a type 8 maintenance packet Target ID = the destination ID of the SerB, is 16 bits if tt = 01 Source ID = the ID of the sending device, is 16 bits if tt = 01 transaction = specifies whether request is read, write and/or response, see sect 4.1.10 of sRIO Input/Output Logical spec rdsize/wrsize = see sect 4.1.2 of sRIO Input/Output Logical spec srcTID = the Transaction ID for sRIO end to end retransmissions Hop Count = Not important to an end point. config_offset = the configuration register address wdptr = part of rdsize/wrsize Payload = 32 bits of data destined to be written to the designated register CRC = 16 bits of CRC
The sRIO maintenance request packet will receive a response packet as shown in Figure 8. The response will be returned to the sender of the request and include a "status" of the request. The status is identified in section 4.1.10 of the sRIO input/Output Logical spec. The SerB shall observe that 0000b indicates "done" and 0111b indicates "error".
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
AckID transaction
rsvd
CRF
prio
tt srcTID
fType
Target ID Hop Count
Source ID config_offset Payload CRC
rdsize/wrsize config_offset Payload
wdptr
rsrv
Figure 8 sRIO Maintenance Response Packet (Type 8)
Other than the status field of the packet, the fields serve the same function as the request packet or are unused. Upon a read request, the Payload is the data content of the selected configuration register. When initiating a Maintenance Response Packet, the hop count will be set to 0xFF. The fields of the response packet are as follows: AckID = Transaction ID for link acknowledgements CRF = The incoming CRF is returned in the response prio = Increased to one higher than the request tt = Same as the request fType = Same as the request (8) Target ID = The Source ID of the request (a simple swap) Source ID = The Target ID of the request (a simple swap) transaction = specifies whether request is read, write and/or response, see sect 4.1.10 of sRIO Input/Output Logical spec status = 0000b means done, 0111b means error
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srcTID = the Transaction ID for sRIO end to end retransmissions (generated at the interface) Hop Count = Set to 0xFF to initiate the hop count Payload = 32 bits of data read from the designated register CRC = 16 bits of CRC
3.4.10 Virtual Channel Handler There is no virtual channel handler in the SerB. Virtual channels do not appear beyond the sRIO interface and have no affect on SerB operation.
3.5 sRIO Control Symbols
The sRIO control symbols are described in the sRIO Part 6: 1x/4x LP-Serial Physical Layer Specification in Chapter 3. Of particular note, these symbols are used to acknowledge all sRIO packets. The SerB shall support the following Stype 0 control symbols. Packet Accepted Packet Retry Packet Not Accepted Status Link Response These control symbols shall be used to acknowledge all incoming sRIO packets and doorbells. Outgoing packets and doorbells shall expect a response and report errors when they occur.
3.6 Use of CRC and CRC Errors
The SerB shall have the capability of using CRC-16 and is defined in the sRIO "1x/4x LP-Serial Physical Layer Specification" in section 2.4.2. The following rules dictate uses of CRC within the SerB: CRC will be CRC-16 with two bytes in size. CRC errors shall be counted. The counts shall be stored and readable through the configuration registers. If retransmission is turned off, a packet with CRC errors shall be dropped. There is no indication a bad packet was received. The CRC error will be logged. The user may use higher level detection to retransmit a section of data. All CRC errors will set the error flag and may cause interrupts or doorbells per the flag configuration. sRIO contains CRC in all packets. CRC suppression is used with the PPS. The minimum packet size when retransmit is turned on is 8 bytes payload.
3.7 Parallel Port Interface
The P-Port is a standard parallel interface that is used to drive QDRII SRAM devices. It has a 36-bit data bus, and other control signals that may be connected to a standard QDRII memory interface. The SerB parallel port options: The SerB may act as a FIFO controller, using an external QDRII-B4 x36 memory as extra storage space that may be allocated to the internal FIFO queue as desired. P-Port may be disabled, either by a pin, or by programming an internal register. The definition of the P-Port interface in this specification is guidance only. The overriding requirement is that the SerB must connect to a QDRII-B4, x36 device.
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
4.0 Data Handling Within the SerB
The S-Port on SerB has the ability to act as an sRIO Endpoint or as an sRIO Bus Master. When the SerB is outputting to an sRIO port, the queue holds the output packet routing information designating the final destination for the data. In the PPS application, the SerB will typically act as an sRIO endpoint (slave), and will respond to commands received through the PPS. In the event that there is an active waterlevel = watermark, the SerB shall become the sRIO bus master to send the multicast packet to the PPS.
4.1 Inputting Data to the Queue
Incoming serial data must be directed to a queue upon entry into the SerB. The incoming packet data carries an identifier that selects a "case scenario" for the data that includes the routing information. In sRIO, the source ID of the data selects the "case scenario" for the data. This is designated at "Case Scenario Mode". 4.1.1 Command Input Buffer There is an input buffer on the SerB that is capable of stacking a small number of commands. There is a separate buffer for read and write commands. It should be noted that commands may become blocked by activity within a queue in the SerB. 4.1.2 Output Buffer There is an output buffer that is capable of stacking output packets on the SerB. In the event that multiple output packets become stacked within the buffer, the higher priority packets will be sent first. A packet that is blocked on the bus for any reason, will prevent the transmission of subsequent same priority packets and lower priority packets until the blocked packet successfully sends, or is discarded. 4.1.3 Writing More Data than can Accept Whenever an attempt is made to write more data to queue than there is space available to accept, the SerB will go through the following stages: When the queue is full, a Full Flag will be set. The flag may then send any interrupts or doorbells to unmasked locations. The incoming data will be accepted in full packets and fill the input buffer on the FIFO port. If the input buffer contains data that it cannot flush into the queue, the data will sit there, preventing the port from writing to the queue. Priority and maintenance packets will not be blocked, but data packets will be blocked If the input buffer also overflows, the incoming packets will be rejected. Only full packets will be accepted. If there is not room to store a complete packet, the entire packet will be rejected. The sender will be notified of the packet rejection. Once the full queue empties enough to allow the data in the input buffer to flow into the queue, the input buffer will again be free to accept more data.
Space Available
The Space Available flag is located in the Full Flag register. It is assumed that if multiple sources are writing to the SerB, they will poll the space available register to see how much room is available for writing. When the space available flag toggles, the flag will be sent to the destination ID within the register and to the port designated by the mask registers. Any multicast will be the responsibility of the user.
4.2 Outputting Data from the Queues
The queue output is dedicated to a port and cannot be reconfigured. The queue is configured with a "Case Scenario" that dictates a destination to which the data is sent. The sending of data is triggered by a waterlevel (event). The configuration registers are used to set up the output mode.
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
4.2.1 Burst Write Start/Stop Address The SerB has the ability to pass large quantities of data with minimal overhead. Data can be passed from sRIO to down stream RIO system memory address as either an SWRITE or NWRITE type packets. To start the data burst, the starting sRIO memory address should be loaded into the Case Scenario Start Address Register, along with the Case Scenario Stop Address Register and an indication of whether to wrap or stop when hitting the maximum address. Case Scenario Next Address Register initially starts off with same value as the Start Address and increments by the quantity of data transmitted with every packet until reaching Stop Address. If a doorbell or interrupt is desired, that may also be programmed. The configuration is "case scenario" based. The start, stop counter, and wrap/stop bits are all configured with the "case" in the configuration register. Therefore any data sent to this case, will increment the counters and addresses checked. It is assumed that the user will be responsible for maintaining data integrity, and will probably use the case for one source of data only. The SerB will form sRIO packets, append the incrementing memory address and send the data out as an sRIO memory data. The memory addresses will continue to increment with subsequent data until all data is transmitted and the port is reconfigured or the address is reset to a new location.
Stop/Wrap on Memory Write
Once sufficient data has entered the SerB to cause the sRIO memory address to reach the stop address programmed into the configuration register, the SerB will do the following: The SerB set the "Mem Stop" bit in the flag register. Unmasked doorbells and interrupts will be sent. The case scenario will be checked for the WRAP/STOP bit setting. - If stop, the remainder of the packet will be transmitted. Stop condition must be cleared before any more data can be transmitted. - If wrap, the address will reset to the start address after the overflow packet is fully transmitted. There will be no attempt to perform the wrap in the middle of a packet. It is the user's responsibility to insure that wrap boundaries concur with packet boundaries.
4.3 Use of Acknowledgements
sRIO has requirements for acknowledgements that must be observed by the SerB and are described in the sRIO specification. Both the ability to enable ACK/NACK and the time-out associated with packet failure may be set by programming the device configuration registers. The receipt of a NACK or the failure to receive an ACK within the allocated time will trigger the retransmission of all packets sent after receipt of the last ACK. When configured to require packet acknowledgements, the following rules apply: Packet is sent with an identifier in the header Additional packets may be sent before acknowledgement is received Packet identifier is incremented for each packet (and wraps) Good packets must be concluded with the End of Good Packet (EGP) marker If a known bad packet is sent, it should be marked End of Bad Packet (EBP) marker. Once a full packet is received, the receiving device must send an acknowledgement or a rejection notice. If sender times out without an acknowledgement, the packet and all subsequent packets are sent again. If rejection notice is received, packet must be retransmitted and all subsequent packets are retransmitted. Packet is rejected if link errors, CRC errors, or EBP code is received If the FIFO fills due to the inability to successfully transmit, it indicates a link down and appropriate flags and priority packets sent (if possible). Note that link level transmissions require that packet acknowledgements be received in the order sent. If a packet is not acknowledged, or acknowledgements are received out of order, it is necessary to retransmit all packets starting after the last packet for which a valid ACK was received. sRIO link acknowledgements require acknowledgments in the order packets were transmitted, but end-to-end acknowledgments may be received in any order. ACK and NACK are performed through link management packets and are not priority packets. ACK and NACK may only be used when "retry-on-error" is enabled.
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
4.4 Idles
When the S-Port is not sending packet data, 8B/10B Idles shall be transmitted, along with any link maintenance packets needed per the protocol spec. Idles received, will be ignored and not result in data being stored within the SerB.
4.5 Case Scenarios
The "Case Scenario" is method used to generate the sRIO packet headers when data is transmitted out of the SerB. The case scenario is established to route every sRIO data packet that is originated by the SerB. A single queue may have data intended for several different destinations as defined by the case scenario. The case scenario may be programmed to be any sRIO command type followed by data, allowing fairly sophisticated command generation with little overhead. While the SerB may program any command into the case scenario, it is not guaranteed that the SerB is capable of fully executing more than the designated command types. The user may be able to use this feature to extend the SerB capabilities. The "Case Scenario Register" must be programmed before use. Every data packet that leaves the SerB must contain an sRIO packet header. The following are the rules describing "Case Scenario". Case Scenario is programmed into the configuration registers. Every data packet originated by the SerB must use a case scenario - sRIO Response packets do not use case scenarios - sRIO Doorbells, messages, and other packets do not use case scenarios The queue is programmed to always select a case scenario for all data that leaves that queue. The destination ID is used to route the packet to the queue. 4.5.1 sRIO Destination IDs for queuing incoming data The SerB itself has a device destination ID, and any incoming sRIO packets that do not contain data (e.g. configuration register updates), should use this device destination ID. The device destination ID is further described in the configuration registers section. It is searchable on the sRIO bus and is programmed during the sRIO "bring up". The queue may be programmed with a destination ID in the configuration register (separate and distinct from the device destination ID). This destination ID is not searchable and not programmed in accordance with the sRIO "bring up" specification. Instead, the register must be programmed using the same methods as most of the other configuration registers. Any data coming over the sRIO port, carrying a destination ID that matches the destination ID for the queue will be loaded into that queue. The destination ID is an eight bit designation within the sRIO packet header. The destination IDs programmed in the configuration registers are also eight bits. The programmed destination ID will be used as the source ID during sRIO transmission. Figure 9 below shows the location of the destination/target ID and the source ID in a typical sRIO packet.
Figure 9 Typical sRIO Packet showing location of Source and Destination IDs
Destination IDs are the means of communication within an sRIO environment. It is required that every sRIO packet have a destination ID and a source ID.
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
4.6 Waterlevel and Watermarks
In the SerB, the "watermark" is a programmable event trigger threshold for the data level associated with a queue. The term "waterlevel" refers to the actual data level within a queue, regardless of whether a "watermark" is used. When the waterlevel in the queue reaches the watermark, an event will take place, depending upon the configuration. The waterlevel and watermarks are used primarily as an indicator to control data flow within a queue. The waterlevels are different than the PAF and PAE flags, because PAE/PAF flags deal in increments of total memory space (1/256th of the queue total) and do not deal with actual data counts. Waterlevels actually count packets or bytes as designated. 4.6.1 Waterlevel Controls Waterlevels are primarily controlled in the configuration registers. The following items are available for controlling the waterlevels: Data in queue is held in packets. Waterlevel - A counter that holds the actual data level in a queue. The count will be in packets. Watermark - This word holds the trigger point for the waterlevel. When the waterlevel reaches this point, the flag will be set. The flag may cause other events to occur (doorbells, interrupts, etc.) A single packet at a time will be sent in their original sizes. Packets will continue to be sent, until the waterlevel drops below the watermark. The remaining data will be held in the queue. Space Available - This is a word in the waterlevel register that indicates how much space is remaining in the queue. The space is in packets. The value of the counter is the total capacity of the queue minus the number of bytes already consumed. It should be noted that when operating as a waterlevel master, the "master mode" only affects the queue output. It is still possible to receive write commands on the queue input. 4.6.2 Example Uses of Waterlevels There are several possible uses of waterlevels and watermarks. A few of the suggested applications are as follows.
Stable Data Level in Queue
This application allows the steady maintenance of a data level in a queue. As data is received, it is stored in the queue until the data level reaches the watermark. Upon the waterlevel reaching the watermark, for every packet received, the queue will transmit an equivalent data item. The following items set up this scenario: The queue is set up to be a master The waterlevel is programmed to count packets The watermark is set to the desired number of packets to be held within the queue at all times The queue sits idle when the packet within the queue is less than the watermark. Packets are received, but not transmitted If the waterlevel reaches or exceeds the watermark, the queue will transmit enough packets to bring the waterlevel back below the watermark.
PPS Specific Use of this Scenario
The basestation application that uses the PPS requires that there be a specific timed delay between the SerB input and output packets. The delay is dependent upon the system requirements, but once the system is configured, it remains fixed. It could be any designated delay, but the maximum in the TI DSP application is 10ms. The quantity of packets that would accumulate within the designated time frame would be dependent upon how many RF cards are used in the basestation. The PPS issues packets to the SerB on a stable time interval, meaning that by using the watermark to designate a quantity of packets, a time interval can be derived from the total. Using the watermark to trigger packet transmissions, the SerB may be used as a programmed packet delay. In the typical PPS application, all packets will be identical in length and at equal time intervals. Usually the PPS will reform packets to all be equal in size regardless of the number of antennas, but in some (rare) PPS applications that have multiple antennas, it may be possible for the PPS to send packets of various sizes to the SerB. This should cause no prob-
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
lems with the waterlevel timer if packet counts are used. It is expected that all antennas will send data at very stable rates, so the combination of two or more sending packets with different sizes will not interfere with the overall timing if the total quantity is adjusted to accommodate the combined larger number.
Packet Ready
This mode may be used to indicate that at least one packet is available in the queue for reading. The flag will toggle, indicating that one or more packets is in the queue. The following is the setup. Queue is programmed to be a slave Waterlevel is programmed to use packets Watermark is set to desired level. The flag masks should be programmed to send the desired interrupt or doorbell to the correct recipients The flag will toggle whenever the packet count in the queue goes from zero to one. The flag will remain active as long as the packet count equals or exceeds one.
Space Available at the Inn
This is the reverse of the Packet Ready scenario. When feeding data into any of the ports, it may be necessary to know that there is room to accept the packet or more data. There are a couple of ways to for the user to accomplish this: Use the same scenario as "Packet Ready" and but set the waterlevel to one full sized packet below the queue size. An interrupt pin could be used as a "space available" pin. There is a flag on the Space Available counter to indicate that there is space for one more full sized packet in the queue. This flag could be used as an interrupt to indicate when the space has fallen below the designated quantity (one packet plus some extra to accommodate latency in shutdown). The space available counter is in the waterlevel register. Use the PAF and PAE flags to generate an interrupt or doorbell. This would give a more general indication of the space available, while preserving the watermark for other uses.
The Flag of Impending Doom
In this scenario, the watermark may be programmed more accurately than the partial flags and could be used as an almost full flag or an almost empty flag. The flag could be used to indicate to the user that immediate action must be taken to avoid overflow or underflow.
4.7 Missing Packet Detection and Packet Replacement
In the wireless basestation application that uses the PPS, a missing packet can cause havoc to the overall system. To help overcome occasional missing packets, a missing packet detection and replacement can be performed. There are four configuration registers that are programmed by the user. The registers contain Memory Start Address, and Memory Stop Address. It is expected in the PPS application that all packets bound for a single DSP will be equal sized and have equal address increments, allowing the Memory Address Increment to be used to detect incoming missing packets. When a packet comes into the PPS, the PPS may segment the packet into 8 segments. The SerB will detect missing packets through the use of the address field in the packet header.
Current Memory Address, Memory Address Increment,
In the PPS application, it is expected that the user will be performing memory writes through sequential addresses. Missing packets may be detected by insuring that the first packet starts on the Memory Start Address and the address associated with every subsequent address matches the previous packet address plus the Memory Address Increment. In other words, the Current Memory Address plus the Memory Address Increment should be the new Current Memory Address of the next incoming packet. If a packet is missed, the address should match the Current Memory Address plus the Memory Address Increment added twice. Upon failing that, it is assumed that more than one packet was lost, or some serious failure occurred and the flag is set in the flag register. Upon a serious failure, the Current Memory Address in the incoming packet should be loaded into to the Current Memory Address register, and the SerB will attempt to compare the new Current Memory Address plus Memory Address Increment with the subsequent packet address. Missing packet detection requires the spacing of the addresses to hold at least two packets. It is not expected that missing packet detection will function properly with only one packet available. If two or more packets are missing, the missing packet detection may require the spacing of the minimum and maximum addresses to allow for storage of at least three packets between the addresses.
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
4.7.1 One Missing Packet Detected If only one packet was lost and the packet that arrived is actually the following packet (detected by the memory address), a marker shall be loaded into the queue to indicate that a missing packet was detected. The incoming packet shall also be loaded into the queue. Two packets shall be transmitted from the queue to attempt to regain the timed data flow (observing transmission rate restrictions). No error is noted and no flag is set. When the missing packet marker reaches the output of the queue, the SerB shall create a dummy packet and transmit it at the time that is designated for the original packet had it not been missing. The DSP receiving the dummy will realize it is a dummy, and can take appropriate action. It follows the normal waterlevel/watermark scheme for transmitting packets. If the stop address is reached, a flag event has occurred and the appropriate flags will toggle. 4.7.2 Two or More Missing Packets Detected In the event that two or more packets are missing, no attempt will be made to reconstruct lost packets. The missing 2 error flag shall be set, which may cause additional doorbells and interrupts. The SerB shall continue to load and transmit data normally, hopefully recovering full operation after the system clears itself of defective data. 4.7.3 Missing Packet Detection Summary The summary for missing packets is as follows: The memory address of each incoming packets shall be checked to insure contiguous addresses. - The memory increment added to the former memory address tells you what the new address should be. - The memory increment does not change in a system, but will be different between systems. Therefore, packets are known length. In the event that an address does not match, it is assumed that there is a missing packet. The memory increment will again be added to the current address and checked with the address of the incoming packet. - If the addresses match, only one packet is missing - If the addresses do not match, two or more packets are missing, or a serious address misalignment has occurred. If one packet is missing - A missing packet marker is loaded into the queue - The incoming packet shall be loaded into the queue - Two packets will automatically be transmitted based on the watermark - The packet interval timer will limit the transmission rate to match the PPS acceptance rate. - When the missing packet location reaches the queue output, a dummy packet (a packet with all zeros in the payload) shall be transmitted to replace the missing packet If more than one packet is missing - No changes will be made to waterlevels - No lost packet markers shall be loaded. - No dummy packets shall be sent - The "Missing 2 Packet" flag shall be set in the Missing 2 programmable flag register. - If the flag is unmasked, a doorbell shall be sent to the destination ID within the register. The content of the doorbell shall be the content designated in the Missing 2 programmable flag register. - The Memory Address of the incoming packet will be loaded into the Current Memory Address register to attempt to realign addresses - Processing will continue as normal on subsequent packets, allowing the DSP to decide if action is needed At the boundary conditions where the memory address exceeds the stop address - On wrap, if the memory increment plus the former memory address exceeds the stop address, the new address will be set to the memory start address. No packet is wrapped in the middle, but the next new packet is set to the memory start address on a wrap. - If the next packet address does not start at the memory start address, a packet is considered missing and should be replaced. - If a second packet fails to match the designated address (start address + increment), the packet will be handled as described above -- "If more than one packet is missing" - The Start and Stop range values must be aligned to the increment boundary (a multiple of the increment). - There must be enough space in the queue to hold more than one packet for the "missing packet detection" to function.
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
4.8 Packet Tally Indicator
In cases where the SerB bursts data to one of the DSPs, the DSP has no way of knowing that it has received the data. The SerB has the ability to send a doorbell indicating that the designated (programmed) number of packets has been sent, so that DSP may act. Bursting must be done on frame boundaries within the DSP/PPS application so that the DSP receives the doorbell on the frame boundary. In PPS, messages may be passed more quickly than data packets, so the message may arrive prior to the data. To avoid this, the DSP must decide what the delay is through the system for each (data and message). The DSP may then program an offset into the SerB registers and a frame size. The TI DSP has no ability to analyze the contents of a doorbell, but instead uses 6 bits of the 16 bit data field as a pointer to an interrupt. The pointer is fixed in the DSP, meaning that the pointer must be programmable in the SerB to match the pointer required by the DSP. Relating this to the SerB, the "case scenario" is used to identify the DSP as a target. Every time a "case scenario" is accessed, the counter within the case scenario shall increment. When the count reaches the maximum programmed for that case, the SerB shall send a doorbell to the destination ID designated in the case scenario, and the count shall reset. The flag register may be used, except the doorbell must be sent regardless of whether previous flags have cleared. Regarding the "offset", aside from initial power up/reset, it is uncertain what the trigger event is that would require an offset. Therefore, the SerB shall provide an offset to the first frame count after power up and upon any reset that clears data. Since the offset is contained in the case scenario, it may be accessed at any time by any of the programming sources and can be adjusted as needed. The "Packet Tally Indicator" Frame Size, Frame Offset, Count, and whether to send a doorbell are contained in each case scenario.
4.9 Packet Interval Timer
The PPS and potentially other devices may not have the ability to accept data at an accelerated rate. The PPS processes incoming data as it arrives, limiting the amount of data that can be accepted in a burst. To solve the problem, a "Packet Interval Timer" has been added to the SerB to regulate the spacing between packets going out the port. There is a separate programmable timer for data packets and priority packets, since they take different routes through the PPS. Every time a packet is sent, the timer is reset and then counts down. Another packet of the same type may not be sent until the timer times out.
4.10 Protocol Translation
Through the sRIO port on the SerB, data may be written to or read from the FIFO. The port also has the capability of initiating data transfers (as a master), and writing data out of the port to another location. In addition, SerB control words may be written into the SerB through the port to configure or to read the status of the device. When using the SerB in two sRIO domains, translation issues arise. It should be noted that the SerB has limited translation capability. Its primary translation function is receiving data, storing data, and subsequently transmitting the data. The ability to pass commands through the SerB is limited. To insure compatibility, there are constraints upon the data. The SerB will handle all link maintenance functions, required responses, retransmissions, and other negotiations. In the PPS application, the SerB is essentially an sRIO to sRIO translator. The SerB receives data in packet form, stores it, and then transmits it at the designated time on the same port. The incoming packet must match the outgoing packet in size. PPS uses only a designated (programmed) packet size.
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
32 of 172
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
5.0 Doorbells and Interrupts
Interrupt pins and packetized Doorbells are used to pass interrupts and messages out of the SerB. Outgoing doorbell packets and interrupts are generated by flags. A flag is considered any event that results in a bit being stored in the "flag register". The content and masks for the flag registers are detailed in Flag and Flag Mask Register section. Events at these locations will cause a flag to be stored at the designated location within the flag register as they occur. In addition to simply residing within the flag register, any flag may cause an interrupt, notifying external devices that a flag event has occurred. This interrupt is considered a "doorbell" and may be issued in one of the following ways: External output pin toggling (two pins, each with a mask). sRIO Type 10 packets sent over S-Port. Each flag register has four mask registers designating which flags should cause the associated "doorbell" or interrupt on the port. A violation of any unmasked flag shall cause the designated interrupt to occur. Of the four mask registers, Mask 1 is associated with S-Port and will cause doorbells to be sent. Mask 3 and Mask 4 are not associated with a port and will cause external interrupt pin 0 and interrupt pin 1o toggle respectively. Mask 2 is reserved for future use. As a default, the flag register mask will not generate any interrupts (full mask). Interrupt generation must be programmed by the mask registers. In the event that multiple flags toggle, the interrupts/doorbells will be generated based upon the priority programmed in the flag registers. In the event that flags have the same priority, the flags will be handled in the order they occurred. In the event that multiple flags with the same priority toggle simultaneously, the flag with lowest address will have priority over flags with higher addresses.
5.1 Doorbell Characteristics
When a flag causes a doorbell, the doorbell includes the following: The register number containing the toggled flag The flag number within the register that toggled The entire unmasked content of the flag register (flags only) sRIO doorbells are limited to a 16-bit payload. 5.1.1 sRIO Flag Doorbell Packet An 8-bit sRIO doorbell packet is shown in Figure 10. The Target ID of the sRIO doorbell is programmed into the flag register causing the doorbell. The Source ID will be the source ID of the doorbell in the SerB. If the doorbell is generated by a queue, the destination ID associated with the queue will be the source ID for the doorbell. If the doorbell is generated by something other than a queue (e.g. a link error), the sRIO generated destination ID of the SerB shall be used as the source ID of the doorbell.
Figure 10 sRIO Doorbell Packet
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet* sRIO 8/16 Bit Destination IDs for sRIO Doorbells
Notes
While typically all transactions with the SerB will be either 8 or 16-bit addresses exclusively, the SerB may be used in systems that mix 8 and 16 bits. Every flag register contains 16 bits that may be used as a destination ID. To define the usage of 8 or 16 bits, every flag register that is capable of sending a doorbell contains a "TT" designation in the flag register that indicates whether the full 16 bits should be used as a destination ID for the doorbell or only the 8 LSBs. The sRIO packet will be formed with the address, based upon the TT bit. In no case will a transaction contain an 8-bit source ID and a 16-bit destination ID (or the reverse) in the same doorbell. This does not exclude the possibility of a queue using 8 bits as the destination ID for the queue, and then generating a doorbell to a 16-bit destination. It does mean that if a user is trying to mix 8 and 16 bit destination IDs, they will need to correlate the 8 LSBs for both.
sRIO Flag Doorbell Payload
The sRIO Flag Doorbell Payload is a maximum of 16 bits. The payload consists of the following 2 bits = Unused 6 bits = Register number of the flag that is causing the doorbell 8 bits = Register contents showing the status of every flag in the register, regardless of whether the flags are masked.
5.2 External Interrupt Pins Int(0) and Int(1)
Each of the two external interrupt pins may be toggled by any unmasked flag. Each pin has its own flag mask available allowing the user to designate the flag or combination of flags that will cause the interrupt pin to toggle. There are two types of flags indicated in the flag register, which are RT (Real Time) and CL (Clearable) flags. When an unmasked RT flag toggles an interrupt pin, the pin will remain active as long as the flag is active and cannot be clear, except by reprogramming the mask. When an unmasked CL flag toggles the pin, the user may reset the flag, and the interrupt indication will be removed from the pin until the flag again toggles or the mask is reprogrammed. It is expected that one of the two pins will be programmed to indicate a generic flag concern, including all flags that may cause concern to the user. The second flag pin would be used to monitor an immediate or frequently used condition, such as "packet ready", meaning that the toggling of the flag generates immediate response without further determination concerning the cause of the interrupt. There is no ability for sRIO to toggle one of the interrupt pins directly through a command. sRIO may toggle a pin indirectly by creating a condition that causes one of the unmasked flags to toggle, subsequently affecting the designated pin. 5.2.1 Clearing Interrupt Clearing an interrupt is accomplished by clearing all flags that are causing the interrupt. Since multiple flags are together in a register and additional flags may toggle after a register has been read, completely clearing a register may clear unrecognized flags. The proper usage of flags and how to clear them, is described in section 8.5, Flag and Flag Mask Registers in the notes of this datasheet. As described, writing a "1b" to a flag clears it. Writing a "0b" to a flag does not affect the flag. This way, any flag may be individually cleared or cleared in combination with other flags in the same register.
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Advanced Datasheet*
Notes
6.0 Device Programming
The operational setup of the SerB is accomplished through the programming of the configuration registers. During power up or master reset, the configuration registers default to a known state based upon the configuration established on the hard-wired pins. After power up, the configuration registers may be further altered through programming. It shall be possible to hard-wire the SerB to have full port functionality and be fully programmable through any of the designated programming methods without relying upon a second programming method. In the priority scheme of configuration, the hard-wired default pin configuration is the dominant configuration during power up or hard reset. The hard-wired inputs will be read on power up or reset, and shall not alter the state of the SerB after completion of power up or reset. The hard-wired configuration may be overwritten through any of the programming schemes, except in a few selected cases (such as designated protocol) where there is no additional programmability. Once fully powered and hard reset is no longer active, the configuration registers may be reprogrammed or altered by several schemes. The configuration register will retain the last programmed configuration regardless of programming method. One programming method is not dominant over the others, except on Master Reset. The methods of device programming are as follows: Hard wired configuration I2 C JTAG sRIO maintenance packets The hard-wired configuration will be the initial default setting for the SerB and forced setting after hard reset. The default configurations are shown in the Configuration Register section. The configuration registers for the SerB are shown in section 8.2 of this datasheet. All configuration registers may be read through I2C, JTAG, and sRIO protocol priority packets. In addition to the listed configuration registers, there are many registers associated with programming sRIO per the sRIO specification. All bits in the configuration registers are readable by any available method. Bits that have restricted write access may still be read by any method.
6.1 Vendor IDs
For sRIO there are three fixed Device IDs. These are available only when sRIO is active and maybe openly accessed by any of the register reading mechanisms. If sRIO is not active, this section of the die is not powered, and the IDs are not available. The sRIO IDs are as follows: The Vendor ID, indicating IDT (assigned by the RapidIO Trade Association) The Device ID, indicating the part type The die signature, indicating date code, revision or other assembly specific information JTAG also has a JTAG vendor ID. All JTAG IDs are accessible only through JTAG.
6.2 Memory Map
Base Address sRIO Configuration Registers 0x000000 - 0x0000FC 0x000100 - 0x00053C 0x000600 - 0x000E3C SerB Configuration Registers 0x018004 0x018008 0x01800C 0x018010 0x018014 Reset & Command Register Serial Port Configuration Register reserved for future use Parallel Port Configuration Register Memory Allocation Register RIO Base Feature Space Registers RIO Extended Feature Space Registers RIO Error Management Space Registers Description
Table 1 SerB Memory Map 35 of 172 March 19, 2007
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IDT 80KSBR200
Advanced Datasheet*
Base Address 0x018018 - 0x01802C 0x018030 0x018034 0x018038 - 0x018054 0x018058 0x01805C - 0x018064 0x018068 - 0x018070 0x018074 - 0x0180C4 0x0180C8 - 0x0180CC 0x0180D0 0x0180D4 - 0x0183FC 0x018400 - 0x018410 0x018414 - 0x01857C 0x018580 - 0x01858C 0x018590 - 0x0185BC 0x0185C0 - 0x0185C4 0x0185C8 0x0185CC 0x0185D0 - 0x0185D8 0x0185DC - 0x01860C 0x018610 - 0x018C2C 0x018C30 0x018C34 - 0x019C00 Flag and Flag Mask Registers 0x019C04 0x019C08 0x019C0C 0x019C10 0x019C14 - 0x019C4C 0x019C50 0x019C54 - 0x019C5C 0x019C60 0x019C64 0x019C68 - 0x019C9C 0x019CA0 0x019CA4 - 0x019CC0 0x019CC4 0x019CC8 0x019CCC 0x019CD0 0x019CD4 - 0x019D0C 0x019D10 0x019D14 - 0x019D1C 0x019D20 0x019D24 S-Port Link Status Flag Register reserved for future use Device Configuration Error Flag Register sRIO DMA Status Register reserved for future use Missing Packet Flag Register reserved for future use FIFO Queue Empty Flag Register FIFO Queue Full Flag Register reserved for future use DSP Interrupt Flag Register reserved S-Port Link Status Mask Register reserved for future use Device Configuration Error Mask Register sRIO DMA Status Mask Register reserved for future use Missing Packet Mask Register reserved FIFO Queue Empty Mask Register FIFO Queue Full Mask Register reserved for future use Lost Packet Replacement Register Source and Destination ID Register reserved for future use PAE-PAF Register reserved for future use Waterlevel/Watermark Control Registers reserved for future use MBIST Registers JTAG Device ID Register reserved Case Scenario Configuration Registers reserved for future use Missing Packet Detection Registers reserved for future use Packet Interval Timer Registers reserved for future use Missing Packet Size Register reserved for future use S-Port Packet XMT/RCV Counter Registers reserved S-Port SERDES Quad Control Register reserved Description
Notes
Table 1 SerB Memory Map 36 of 172 March 19, 2007
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IDT 80KSBR200
Advanced Datasheet*
Base Address 0x019D28 - 0x019D5C 0x019D60 0x019D64 - 0x019E0C 0x019E10 0x019E14 - 0x019E4C 0x019E50 0x019E54 - 0x019E5C 0x019E60 0x019E64 - 0x019ECC 0x019ED0 0x019ED4 - 0x019F0C 0x019F10 0x019F14 - 0x019F1C 0x019F20 reserved Missing Packet Address Log Register 1 reserved Tally Doorbell Flag Register reserved Missing Packet Programmable Flag Register reserved DSP Interrupt Mask Register reserved Tally Doorbell Mask Register reserved Missing Packet Programmable Mask Register reserved Missing Packet Address Log Registers 2 Description
Notes
Table 1 SerB Memory Map
6.3 Configuration Register Programming and Reset
There are multiple types and severity of reset capabilities. Many of the resets involve loading the configuration registers, or clearing values contained in the registers. The various resets may be performed through the following mechanisms:

External pins sRIO control symbols. sRIO type 8 maintenance packets JTAG and I2C commands
Multiple types of resets may be generated using the reset mechanisms. The following items list the various resets, the mechanism(s) to force the reset, the effects of the reset and other reset information:
Master Reset - Performed after power on and anytime a full reset is needed. - - - - - - - - - - Pin based reset or sRIO control symbol only. Any shadow registers are programmed to the state required by the hard-wired configuration pins. All configuration registers programmed to the state required by the hard-wired configuration pins. Any registers that do not have default values are cleared. All memory will be cleared. All flag registers will be cleared. All mask registers are set to fully masked. All Error counters and status registers will be cleared (not set to a programmed value). All PLLs will be reset. Any existing state machines will be initialized to a known state. Any changes are immediate
Partial Reset - Performed anytime and affects all registers. (An example of this type of reset would be the changing of a port data rate). - - - - - - - sRIO maintenance packet reset, JTAG, or I2C based reset. This reset is performed by "hitting" the reset configuration register. Shadow registers are not affected. Configuration registers with shadow registers are programmed to the shadow values. Configuration registers without shadow registers are cleared. All memory will be cleared All flag registers will be cleared. All mask registers are set to fully masked. All Error counters and status registers will be cleared (not set to a programmed value).
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IDT 80KSBR200
Advanced Datasheet*
Notes
- - -
All PLLs will be reset. Any existing state machines will be initialized to a known state. Any changes are immediate, except JTAG and I2C will perform the change at the designated command
Load Configuration - Identical to "Partial Reset" except ports and PLLs are not reset.
6.3.1 Programming
Configuration Register Reset (registers without shadows) - These resets may be performed anytime on the fly and they affect only the designated register. They are performed by loading the individual register with a new value. (Example of the registers affected include the destination IDs). - - - - - - - - sRIO maintenance packet. The registers may not be programmed through JTAG, or I2C. Shadow registers and configuration registers with shadows are not affected. Memory is not affected Flag registers may be individually cleared using this method. Mask registers are part of the flag register and will be affected along with any writing to the flag registers for clearing. Designated error counters and status registers will be cleared (not set to a programmed value). PLLs are not affected Any existing state machines are not affected, except possibly as a result of the register changing. Any changes are immediate
Shadow Register Programming - These resets may be performed anytime on the fly and they affect only the designated shadow register. They are performed by loading the individual register with a new value. - - - - - - - - Programming may be done through sRIO maintenance packets, JTAG or I2C. Only shadow registers are affected. Memory is not affected Flag and Flag Mask registers are not affected. Error counters and status registers are not affected. PLLs are not affected No existing state machines are affected. There is no immediate effect on any configuration register from programming a shadow register. To load the results of the programming into the designated configuration registers, a "Load Configuration" reset must subsequently be performed.
Flag Register Reset - These resets may be performed anytime on the fly and they affect only the designated register. - - Performed with sRIO maintenance packets. Flag registers are cleared by writing to them. Writing the Wr32 bit within the register designates whether the write to a flag register is intended to alter the entire register, including destination IDs, or simply clear flags. Flags may be cleared by writing a "1" to them. Any flag that is written with a "0" will remain unchanged. Some flag registers contain real time values, indicated by "RT" in the flag register section. These values cannot be cleared except by affecting the source of the flag. A new doorbell or interrupt will not be generated if the RT flag is active. Error counters and status registers may be associated with flag registers and will be cleared if written to. JTAG and I2C may read the registers, but cannot clear the flag registers, except through a load configuration type reset. Any changes are immediate
- - - -
6.3.2 Clearing Flags Flags are cleared by the various "resets" associated with the SerB. The methods of clearing flags are described in section 6.3, of this datasheet. In summary, any flag may be cleared by Master Reset, a Load Configuration, or by writing to the flag register. Any mask register may be programmed by writing to it, but it won't be affected by clearing a flag register.
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IDT 80KSBR200
Advanced Datasheet*
Notes
Any "Real Time" flag, indicated by RT in the following flag register tables, indicates the current condition of the flagcausing event and cannot be cleared. No new doorbells or interrupts will be generated as a result of the write to a flag register containing an RT flag. To generate a new doorbell or interrupt, at least one flag in the register must de-assert and reassert. Clearable flags are indicated by CL in the following flag register tables. These flags assert and lock whenever a flag event occurs. They must be cleared by one of the designated reset methods. These flags represent highly transient conditions, so in most cases the flag causing condition has disappeared prior to the clearing. In the event that the flag causing condition is active at the time of the clearing, and the flag is immediately reasserted, a new doorbell or interrupt will be generated. 6.3.3 Flag Masks Flag masks default to fully masked upon a Master Reset or Load Configuration reset. The flag mask registers are considered configuration registers and are individually programmed the same way as other configuration registers. The flag mask registers have no shadow registers, so they can be programmed "on the fly".
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IDT 80KSBR200
Advanced Datasheet*
Notes
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Advanced Datasheet*
Notes
7.0 Error Management
The SB handles errors in two ways. The errors are defined as either errors that fall under the "RapidIO Part 8: Error Management Extensions Specification" or errors that do not. The configuration registers associated with errors are found in the RapidIO Part 8: Error Management Extensions Specification section 2.3, outlines the required registers for error management. This section is focused on errors and status information in addition to the minimum required by the RIO specification.
7.1 sRIO Errors and Error Handling
This section describes how the logical and physical layers will detect and react to RIO errors. The action of the SerB upon notification off any of these errors is described minimally; for detail see Interrupt Generation. Reference RIO Interconnect Specification Part 8 (Error Management Extensions Specifications) for more detail on specific errors described below. RIO errors are classified under three categories: Recoverable errors Notification errors Fatal errors 7.1.1 Recoverable Errors These errors are non-fatal transmission errors (such as corrupt packet or control symbols, and general protocol errors) that RIO supports hardware detection of and a recovery mechanism for, as described in the RIO specification. In these cases, the appropriate bit is set in the Port n Error Detect CSR. Only the packet containing the first detected recoverable error that is enabled for error capture (by Port n Error Enable CSR) will be captured in the Port n Error Capture CSRs. No interrupt is generated or actions required for a recoverable error. Recoverable errors are detected in the physical layer only. 7.1.2 Notification Errors These errors are non-recoverable non-fatal errors detected by RIO (such as Degraded Threshold, Port-Write received, and all logical/transport layer (LTL) errors captured). Because they are non-recoverable (and in some cases have caused a packet to be dropped), notification by interrupt is available. However, because they are non-fatal, response to the interrupt is not crucial to port performance; i.e., the port is still functional. When a notification error is detected, the appropriate bit is set in the error-specific register, an interrupt is generated, and in some cases, the error is captured. The Degraded Threshold error also causes the port to request training (parallel only) with the hope that port performance will improve. In all cases, the RIO port continues operating. Notification errors are detected in both the physical and logical layer. 7.1.3 Fatal Errors SerB detects two fatal errors: Exceeded failed threshold Exceeded consecutive retry threshold In these cases, the port has failed because its Recoverable Error Rate has exceeded a predefined failed threshold or because it has received too many packet retries in a row. In the first case, GRIO will set the Output Failed-encountered bit in the Port n Error and Status CSR; the RIO output hardware may or may not stop (based on Stop-on-Port-FailedEncounter-Enable and Drop-Packet-Enable bits). In the second case, RIO will set the Retry Counter Threshold Trigger Exceeded bit in the Port n Implementation Error CSR; the RIO hardware will continue to operate. In both cases, an interrupt is generated, and while the port will continue operating at least partially, a system-level fix (such as reset) is recommended to clean up RIO's internal queues and resume normal operation. Fatal errors are detected in the physical layer only.
7.2 System Software Error Notification
System software is notified of logical, transport, and physical layer errors in two ways. An interrupt is issued to the local system by means of interrupt pins if enabled, or a Maintenance port-write operation issued by SerB. For specifics on interrupt mechanism, see section 5, Doorbells and Interrupt of this datasheet. Maintenance port-write operations are sent to a
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IDT 80KSBR200
Advanced Datasheet*
Notes
predetermined system host (defined in the Port-write Target deviceID CSR). SerB sets the Port-write Pending status bit in the Port 0 Error and Status CSR. A 16 byte data payload of the Maintenance Port-write packet contains the contents of several CSR, as shown in table below. Once System Software receives an Port-write operation, it indicates that it has seen the port-write by clearing the Port-write Pending status bit in the Port 0 Error and Status CSR. The Component Tag CSR is defined in the RapidIO Part 3: Common Transport Specification, and is used to uniquely identify the reporting device within the system. A Port ID field contains all 0's indicating port 0, the Logical/Transport Layer Error Detect CSR, and the Port 0 Error Detect CSR are used to describe the encountered error condition.
Data Payload Byte Offset 0x0 0x4 0x8 0xC
Word
Component TAG CSR Port 0 Error Detect CSR Implementation Specific Logical/Transport Layer Error Detect CSR PortID(byte)
Table 2 Port-write Packet Data Payload for Error Reporting
7.3 sRIO Errors Supported
7.3.1 Physical Layer Errors Table below lists all the RIO link errors detected by the SerB physical layer and the actions taken by SerB. The Error Enable column lists the control bits that may disable the error checking associated with a particular error (if blank, error checking cannot be disabled). The Cause Field column indicates what cause field will be used with the associated packetnot-accept control symbol for Input Error Recovery. The EME Error Enable/Detect column indicates which bit of the P0ERECSR allows the error to increment the Error Rate Counter and lock the Port 0 Error Capture registers, and likewise which bit of the P0EDCSR is set when the error has been detected. Table 4 below, Physical RIO Threshold Response, lists SerB behavior after exceeding certain preset limits (Degraded Threshold, Failed Threshold, Retry Threshold).
Physical RIO Errors Detected
EME Error Type Delineation Error EME Error Enable / Detect DE
Error
Error Enable
SerB action
Cause Field
Received character had a disparity error.
Enter Input Error Stopped. Enter Output Error Stopped. Enter Input Error Stopped. Enter Output Error Stopped. Enter Input Error Stopped. Enter Output Error Stopped. Enter Input Error Stopped. Enter Output Error Stopped.
5: Received invalid/illegal character 5: Received invalid/illegal character 5: Received invalid/illegal character 5: Received invalid/illegal character
Received an invalid character, or valid but illegal character
The four contol character bits associated with the received symbol do not make sense (not 0000, 1000, 1111). Control symbol does not begin with an /S/ or /PD/ control character.
Table 3 Physical RIO Errors Detected
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IDT 80KSBR200
Advanced Datasheet*
EME Error Type Received corrupt control symbol Received packet with unexpected ackID Received packet with bad CRC Received packet exceeds 276 Bytes Protocol Error (unexpected packet/control symbol received) EME Error Enable / Detect CCS
Notes
Error
Error Enable
SerB action
Cause Field
Received a control symbol with a bad CRC
P0PCR[CCC] enables detect.
Enter Input Error Stopped. Enter Output Error Stopped. Enter Input Error Stopped.
2. Received a control symbol with bad CRC 1: Received unexpected ACKID on packet 4: Bad CRC on packet 7/31: General error
Received packet with unexpected ackID (out-of-sequence ACKID). Received packet with a bad CRC value. Received packet which exceeds the maximum allowed size by the RIO spec. Packet data received w/o previous SOP control symbol. Received an EOP control symbol when there is no packet being received. Received a stomp control symbol when there is no packet being received. Received packet that is < 64 bits. Received a Restart-from-retry control symbol when in the "OK" state. Received packet with embedded idles. Received a non-maintenance packet when non-maintenance packet reception is stopped. Non-maint. packet reception is stopped when "Input Port Enable" = 0. All packet reception is stopped when Port Lockout bit is set. P0PCR[CCP] enables detect.
UA
Enter Input Error Stopped. Enter Input Error Stopped.
CRC
EM
Enter Input Error Stopped. Enter Input Error Stopped. Enter Input Error Stopped. Enter Input Error Stopped. Enter Input Error Stopped. Enter Input Error Stopped. Enter Input Error Stopped.
31: General error 7/31: General error 7/31: General error 7/31: General error 7/31: General error 31: General error 3. Non-maintenance packet reception is stopped 3. Non-maintenance packet reception is stopped
PE
Not Captured
Any packet received while Port Lockout bit is set.
Enter Input Error Stopped.
Not Captured
Received a Link request control symbol before servicing previous link request. Received an ACK (accepted or retry) control symbol with an unexpected ACKID. Received packet-not-accepted ACK control symbol
Not Detected.
Enter Output Error Stopped.
Received ack. control symbol with unexpected ackID Received packet-notaccepted symbol
AUA
Enter Output Error Stopped.
PNA
Table 3 Physical RIO Errors Detected
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IDT 80KSBR200
Advanced Datasheet*
EME Error Type Non-outstanding ackID Unsolicited ACK symbol EME Error Enable / Detect NOA
Notes
Error
Error Enable
SerB action
Cause Field
Link_response received with an ackID that is not outstanding. Received an ACK (accepted, or retry) control symbol when there are no outstanding packets Received packet ACK (accepted) for a packet whose transmission has nor finish. Received a Link response control symbol when no outstanding request. An ACK control symbol is not received within the specified time-out interval. A Link response is not received within the specified time-out interval. PLTOCCSR [TV] > 0 enables detect. PLTOCCSR [TV] > 0 enables detect.
Enter Output Error Stopped. Enter Output Error Stopped. Enter Output Error Stopped. Enter Output Error Stopped. Enter Output Error Stopped. (re-) Enter Output Error Stopped.
UCS
Link time-out
LTO
Table 3 Physical RIO Errors Detected Physical RIO Threshold Response
Error Error Enable SerB action Notification Errors Error Rate Counter has exceeded the Degraded Threshold. P0ERTCSR[ERDTT]> 0 & any bit in P0EECSR enables detect and interrupt generation. Generate Interrupt. Parallel port will initiate Maintenance Training if TODTEN bit is set. Continue to operate normally. Fatal Errors Consecutive Retry Counter has exceeded the Retry Counter Threshold Trigger. Error Rate Counter has exceeded the Failed Threshold. PRETCR[RET]>0 enables detect and interrupt generation. P0ERTCSR[ERFTT]> 0 & any bit in P0EECSR enables detect and interrupt generation. Generate Interrupt. Port will be in priority order Consecutive Retry Threshold Failed Threshold P0IECSR [RETE] Write 1 to P0IECSR [RETE] Write 1 to P0ESCSR [OFE] Degraded Threshold P0ESCSR [ODE] Write 1 to P0ESCSR [ODE] EME Error Type Error Detect Interrupt Clear
Generate Interrupt. Port behavior depends on P0CCSR[SPF] and P0CCSR[DPE] -port can continue transmitting packets or can stop sending output packets, keeping or dropping them. Parallel port will initiate Full Training if TOFTEN bit is set.
P0ESCSR [OFE]
Table 4 Physical RIO Threshold Response
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IDT 80KSBR200
Advanced Datasheet*
Notes
7.3.2 Logical Layer Errors Table below lists all the errors detected by the SerB logical layer and the actions taken by SerB. Note that when the SerB action includes sending an error response to either UL or RIO, an error response is only sent if the original transaction was a request that required a response. Otherwise, no error response is sent. When dealing with multiple errors, discard of packet has higher priority than error response. Here, error checking is listed based on the type of transaction and table also lists the action taken for particular error.
Errors for NRead Transaction
Interrupt Generated if enable bit set on LTLEECSR Bit 4: ITD
Error
Status Bit set on LTLEDCSR
RIO Error Response Generated
Logical/Transport Layer Capture Register
Comments
Priority Priority of Read transaction is 3
Bit 4: ITD
No
Using the incoming RIO packet, for Small Transport type packet; LTLACCSR[XA] = packet bits [78:79], LTLACCSR[A] = packet bits [48:76], LTLDIDCCSR[DIDMSB] = 0's, LTLDIDCCSR[DID] = packet bits [16:23], LTLDIDCCSR[SIDMSB] = 0's, LTLDIDCCSR[SID] = packet bits [24:31], LTLCCCSR[FT] = packet bits [12:15], LTLCCCSR[TT] = packet bits [32:35] For Large Transport type packets; LTLACCSR[XA] = packet bits [94:95], LTLACCSR[A] = packet bits [64:92], LTLDIDCCSR[DIDMSB] = packet bits[16:23], LTLDIDCCSR[DID] = packet bits [24:31], LTLDIDCCSR[SIDMSB] = packet bits[32:39], LTLDIDCCSR[SID] = packet bits [40:47], LTLCCCSR[FT] = packet bits [12:15], LTLCCCSR[TT] = packet bits [48:51]
RIO packet dropped
TransportType Received reserved TT Received TT which is not enabled
Bit 28: TSE
Bit 28: TSE
No
Same as previous entry
RIO packet is dropped
Table 5 Hardware Errors for NRead Transaction
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IDT 80KSBR200
Advanced Datasheet*
Interrupt Generated if enable bit set on LTLEECSR Bit 5: ITTE
Notes
Error
Status Bit set on LTLEDCSR
RIO Error Response Generated
Logical/Transport Layer Capture Register
Comments
DestID DestID does not match this port's DeviceID or Alternate DeviceID when enabled SourceID Not checked for error TransactionType Received RIO packet with reserved TType for this ftype RdSize Not checked for error SrcTID Not checked for error Address: WdPtr:Xambs Beginning address matches LCSBA1CSR with non 32 bit read request. (Performed only when ttype == 4'b0100) Header Size Header size is not 12 Bytes for small Transport packet or not 16 Bytes for Large Transport packet. (Large Transport packet has 14 valid bytes and two bytes of 0's. Padding of 0's is not checked).
Bit 5: ITTE
Yes
Same as previous entry
--
Bit 4: ITD
Bit 4: ITD
Yes
Same as previous entry
Bit 4: ITD
Bit 4: ITD
Yes
Same as previous entry
--
Bit 4: ITD
Bit 4: ITD
Yes
Same as previous entry
--
Table 5 Hardware Errors for NRead Transaction 46 of 172 March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Interrupt Generated if enable bit set on LTLEECSR
Notes
Error
Status Bit set on LTLEDCSR
RIO Error Response Generated
Logical/Transport Layer Capture Register
Comments
PayloadSize Not Applicable
Table 5 Hardware Errors for NRead Transaction Errors for Maintenance Read/Write Request Transaction
Interrupt Generated if enable bit set on LTLEECSR Bit 4: ITD
Error
Status Bit set on LTLEDCSR
RIO Error Response Generated
Logical/Transport Layer Capture Register
Comments
Priority Priority of maintenance read or write request transaction is 3
Bit 4: ITD
No
Using the incoming RIO packet, for Small Transport type packet; LTLACCSR[XA] = packet bits [78:79], LTLACCSR[A] = packet bits [48:76], LTLDIDCCSR[DIDMSB] = 0's, LTLDIDCCSR[DID] = packet bits [16:23], LTLDIDCCSR[SIDMSB] = 0's, LTLDIDCCSR[SID] = packet bits [24:31], LTLCCCSR[FT] = packet bits [12:15], LTLCCCSR[TT] = packet bits [32:35] For Large Transport type packets; LTLACCSR[XA] = packet bits [94:95], LTLACCSR[A] = packet bits [64:92], LTLDIDCCSR[DIDMSB] = packet bits[16:23], LTLDIDCCSR[DID] = packet bits [24:31], LTLDIDCCSR[SIDMSB] = packet bits[32:39], LTLDIDCCSR[SID] = packet bits [40:47], LTLCCCSR[FT] = packet bits [12:15], LTLCCCSR[TT] = packet bits [48:51]
RIO packet dropped
Table 6 Hardware Errors for Maintenance Read/Write Request Transaction
47 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Interrupt Generated if enable bit set on LTLEECSR Bit 28: TSE
Notes
Error
Status Bit set on LTLEDCSR
RIO Error Response Generated
Logical/Transport Layer Capture Register
Comments
TransportType Received reserved TT Received TT which is not enabled DestID DestID does not match this port's DeviceID or Alternate DeviceID when enabled SourceID Not checked for error TransactionType Received RIO packet with reserved TType for this ftype RdSize Read/Write request size is not for 4 bytes SrcTID Not checked for error HopCount Not checked for error Config Offset Not checked for error
Bit 28: TSE
No
Same as previous entry
RIO packet is dropped
Bit 5: ITTE
Bit 5: ITTE
Yes
Same as previous entry
--
Bit 4: ITD
Bit 4: ITD
Yes
Same as previous entry
--
Bit 4: ITD
Bit 4: ITD
Yes
Same as previous entry
--
Table 6 Hardware Errors for Maintenance Read/Write Request Transaction
48 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Interrupt Generated if enable bit set on LTLEECSR Bit 4: ITD
Notes
Error
Status Bit set on LTLEDCSR
RIO Error Response Generated
Logical/Transport Layer Capture Register
Comments
Header Size Header size is not 12 Bytes for small Transport packet or not 16 Bytes for Large Transport packet. (Large Transport packet has 14 valid bytes and two bytes of 0's. Padding of 0's is not checked). PayloadSize Write request with payload not equal to 8 bytes Read request with payload not 0 bytes
Bit 4: ITD
Yes
Same as previous entry
--
Bit 4: ITD
Bit 4: ITD
Yes
Same as previous entry
--
Table 6 Hardware Errors for Maintenance Read/Write Request Transaction
49 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet* Errors for RIO Write class Transactions
Interrupt Generated if enable bit set on LTLEECSR Bit 4: ITD
Notes
Error
Status Bit set on LTLEDCSR
RIO Error Response Generated
Logical/Transport Layer Capture Register
Comments
Priority Nwrite_r, Nwrite transaction has priority 3
Bit 4: ITD
No
Using the incoming RIO packet, for Small Transport type packet; LTLACCSR[XA] = packet bits [78:79], LTLACCSR[A] = packet bits [48:76], LTLDIDCCSR[DIDMSB] = 0's, LTLDIDCCSR[DID] = packet bits [16:23], LTLDIDCCSR[SIDMSB] = 0's, LTLDIDCCSR[SID] = packet bits [24:31], LTLCCCSR[FT] = packet bits [12:15], LTLCCCSR[TT] = packet bits [32:35] For Large Transport type packets; LTLACCSR[XA] = packet bits [94:95], LTLACCSR[A] = packet bits [64:92], LTLDIDCCSR[DIDMSB] = packet bits[16:23], LTLDIDCCSR[DID] = packet bits [24:31], LTLDIDCCSR[SIDMSB] = packet bits[32:39], LTLDIDCCSR[SID] = packet bits [40:47], LTLCCCSR[FT] = packet bits [12:15], LTLCCCSR[TT] = packet bits [48:51]
RIO packet dropped
TransportType Received reserved TT Received TT which is not enabled DestID DestID does not match this port's DeviceID or Alternate DeviceID when enabled SourceID Not Applicable
Bit 28: TSE
Bit 28: TSE
No
Same as previous entry
RIO packet is dropped
Bit 5: ITTE
Bit 5: ITTE
Yes for Nwrite_r, No for Nwrite
Same as previous entry
--
Table 7 Hardware Errors for RIO Write class Transactions 50 of 172 March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Interrupt Generated if enable bit set on LTLEECSR Bit 9: UT
Notes
Error
Status Bit set on LTLEDCSR
RIO Error Response Generated
Logical/Transport Layer Capture Register
Comments
TransactionType Received RIO packet for Atomic testand-swap transaction Received RIO packet with reserved TType for this ftype Packet is treated as Nwrite Transaction WrSize WrSize request is for one of reserved sizes SrcTID Not checked for error Address: WdPtr:Xambs Nwrite_r address matches LCSBA1CSR with non 32 bit read request. (Performed only when TType == 4'b0101) Header Size Header size is not 12 Bytes for small Transport packet or not 16 Bytes for Large Transport packet. (Large Transport packet has 14 valid bytes and two bytes of 0's. Padding of 0's is not checked).
Bit 9: UT
Yes
Same as previous entry
--
Bit 4: ITD
Bit 4: ITD
Yes for Nwrite_r, No for Nwrite
Same as previous entry
--
Bit 4: ITD
Bit 4: ITD
Yes for Nwrite_r
Same as previous entry
--
Bit 4: ITD
Bit 4: ITD
Yes for Nwrite_r, No for Nwrite
Same as previous entry
--
Table 7 Hardware Errors for RIO Write class Transactions 51 of 172 March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Interrupt Generated if enable bit set on LTLEECSR Bit 4: ITD
Notes
Error
Status Bit set on LTLEDCSR
RIO Error Response Generated
Logical/Transport Layer Capture Register
Comments
PayloadSize Payload is greater than that indicated by {wdptr:wrsize} field, payload is not double word aligned or does not have any payload.
Bit 4: ITD
Yes for Nwrite_r, No for Nwrite
Same as previous entry
--
Table 7 Hardware Errors for RIO Write class Transactions
52 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet* Errors for SWrite class Transactions
Interrupt Generated if enable bit set on LTLEECSR Bit 4: ITD
Notes
Error
Status Bit set on LTLEDCSR
RIO Error Response Generated
Logical/Transport Layer Capture Register
Comments
Priority Swrite transaction is priority 3
Bit 4: ITD
No
Using the incoming RIO packet, for Small Transport type packet; LTLACCSR[XA] = packet bits [78:79], LTLACCSR[A] = packet bits [48:76], LTLDIDCCSR[DIDMSB] = 0's, LTLDIDCCSR[DID] = packet bits [16:23], LTLDIDCCSR[SIDMSB] = 0's, LTLDIDCCSR[SID] = packet bits [24:31], LTLCCCSR[FT] = packet bits [12:15], LTLCCCSR[TT] = packet bits [32:35] For Large Transport type packets; LTLACCSR[XA] = packet bits [94:95], LTLACCSR[A] = packet bits [64:92], LTLDIDCCSR[DIDMSB] = packet bits[16:23], LTLDIDCCSR[DID] = packet bits [24:31], LTLDIDCCSR[SIDMSB] = packet bits[32:39], LTLDIDCCSR[SID] = packet bits [40:47], LTLCCCSR[FT] = packet bits [12:15], LTLCCCSR[TT] = packet bits [48:51]
RIO packet dropped
TransportType Received reserved TT Received TT which is not enabled DestID DestID does not match this port's DeviceID or Alternate DeviceID when enabled SourceID Not Applicable
Bit 28: TSE
Bit 28: TSE
No
Same as previous entry
RIO packet is dropped
Bit 5: ITTE
Bit 5: ITTE
No
Same as previous entry
RIO packet is dropped
Table 8 Hardware Errors for SWrite class Transactions 53 of 172 March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Interrupt Generated if enable bit set on LTLEECSR Bit 4: ITD
Notes
Error
Status Bit set on LTLEDCSR
RIO Error Response Generated
Logical/Transport Layer Capture Register
Comments
PayloadSize Payload size is not in double word aligned, has exceeded 256 bytes or has no payload.
Bit 4: ITD
No
Same as previous entry
RIO packet is dropped
Table 8 Hardware Errors for SWrite class Transactions Errors for Maintenance Response Transactions
Interrupt Generated if enable bit set on LTLEECSR Bit 4: ITD
Error
Status Bit set on LTLEDCSR
RIO Error Response Generated
Logical/Transport Layer Capture Register
Comments
Priority Response priority is not higher than RIO maintenance request priority
Bit 4: ITD
No
Using the incoming RIO packet, for Small Transport type packet; LTLACCSR[XA] = packet bits [78:79], LTLACCSR[A] = packet bits [48:76], LTLDIDCCSR[DIDMSB] = 0's, LTLDIDCCSR[DID] = packet bits [16:23], LTLDIDCCSR[SIDMSB] = 0's, LTLDIDCCSR[SID] = packet bits [24:31], LTLCCCSR[FT] = packet bits [12:15], LTLCCCSR[TT] = packet bits [32:35] For Large Transport type packets; LTLACCSR[XA] = packet bits [94:95], LTLACCSR[A] = packet bits [64:92], LTLDIDCCSR[DIDMSB] = packet bits[16:23], LTLDIDCCSR[DID] = packet bits [24:31], LTLDIDCCSR[SIDMSB] = packet bits[32:39], LTLDIDCCSR[SID] = packet bits [40:47], LTLCCCSR[FT] = packet bits [12:15], LTLCCCSR[TT] = packet bits [48:51]
RIO packet dropped and ignored
Table 9 Hardware Errors for Maintenance Response Transactions
54 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Interrupt Generated if enable bit set on LTLEECSR Bit 28: TSE
Notes
Error
Status Bit set on LTLEDCSR
RIO Error Response Generated
Logical/Transport Layer Capture Register
Comments
TransportType Received reserved TT Received TT which is not enabled DestID DestID does not match this port's DeviceID or Alternate DeviceID when enabled SourceID Does not match the request's DestID TransactionType Received RIO packet with reserved TType for this ftype HopCount Not checked for error Status Is not "Done" or "Error" Not "Done" status for "read_response " transaction type with payload "Error" status with payload Status Error Response TargetTID No outstanding transaction for this TargetTID
Bit 28: TSE
No
Same as previous entry
RIO packet is dropped and ignored
Bit 5: ITTE
Bit 5: ITTE
Yes
Same as previous entry
RIO packet is dropped and ignored
Bit 8: UR
Bit 8: UR
No
Same as previous entry
RIO packet is dropped and ignored
Bit 4: ITD
Bit 4: ITD
No
Same as previous entry
RIO packet is dropped and ignored
Bit 4: ITD
Bit 4: ITD
No
Same as previous entry
RIO packet is dropped and ignored
Bit 0: IER
Bit 0: IER
No
Same as previous entry except error capture is done from original request Same as previous entry
--
Bit 8: UR
Bit 8: UR
No
RIO packet is dropped and ignored
Table 9 Hardware Errors for Maintenance Response Transactions 55 of 172 March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Interrupt Generated if enable bit set on LTLEECSR Bit 4: ITD
Notes
Error
Status Bit set on LTLEDCSR
RIO Error Response Generated
Logical/Transport Layer Capture Register
Comments
Header Size Maintenance Read response - total payload size with done status is not greater than 4 Bytes. Maintenance Write response - total header size is less than 12 Bytes for Small Transport packet or is less than 16 Bytes for Large Transport packet. PayloadSize Maintenance write response has payload Maintenance read response with done status and payload not matching valid request size or request size for the response is invalid. Packet Response Time-out Response is not received by configured time.
Bit 4: ITD
No
Same as previous entry
RIO packet is dropped and ignored
Bit 4: ITD
Bit 4: ITD
No
Same as previous entry
RIO packet is dropped and ignored
Bit 7: PRT
Bit 7: PRT
No
Same as previous entry except error capture is done from original request
--
Table 9 Hardware Errors for Maintenance Response Transactions
56 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet* Error for Response Transaction
Interrupt Generated if enable bit set on LTLEECSR Bit 4: ITD
Notes
Error
Status Bit set on LTLEDCSR
RIO Error Response Generated
Logical/Transport Layer Capture Register
Comments
Priority Response priority is not higher than RIO request priority
Bit 4: ITD
No
Using the incoming RIO packet, for Small Transport type packet; LTLACCSR[XA] = packet bits [78:79], LTLACCSR[A] = packet bits [48:76], LTLDIDCCSR[DIDMSB] = 0's, LTLDIDCCSR[DID] = packet bits [16:23], LTLDIDCCSR[SIDMSB] = 0's, LTLDIDCCSR[SID] = packet bits [24:31], LTLCCCSR[FT] = packet bits [12:15], LTLCCCSR[TT] = packet bits [32:35] For Large Transport type packets; LTLACCSR[XA] = packet bits [94:95], LTLACCSR[A] = packet bits [64:92], LTLDIDCCSR[DIDMSB] = packet bits[16:23], LTLDIDCCSR[DID] = packet bits [24:31], LTLDIDCCSR[SIDMSB] = packet bits[32:39], LTLDIDCCSR[SID] = packet bits [40:47], LTLCCCSR[FT] = packet bits [12:15], LTLCCCSR[TT] = packet bits [48:51]
RIO packet dropped and ignored
TransportType Received reserved TT for this FType Received TT which is not enabled DestID DestID does not match this port's DeviceID or Alternate DeviceID when enabled
Bit 28: TSE
Bit 28: TSE
No
Same as previous entry
RIO packet is dropped and ignored
Bit 5: ITTE
Bit 5: ITTE
No
Same as previous entry
RIO packet is dropped and ignored
Table 10 Hardware Error for Response Transactions
57 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Interrupt Generated if enable bit set on LTLEECSR Bit 8: UR
Notes
Error
Status Bit set on LTLEDCSR
RIO Error Response Generated
Logical/Transport Layer Capture Register
Comments
SourceID Does not match the request's DestID TransactionType Received RIO packet with reserved TType IO read response does not correspond to an outstanding valid IO read request. IO write response does not correspond to an outstanding valid IO write request. Status IO transaction Is not "Done" or "Error" Transaction type of "Response_wit h_data" and status is not done. Status IO Error Response TargetTID No outstanding transaction for this TargetTID
Bit 8: UR
No
Same as previous entry
RIO packet is dropped and ignored
Bit 4: ITD
Bit 4: ITD
No
Same as previous entry
RIO packet is dropped and ignored
Bit 4: ITD
Bit 4: ITD
No
Same as previous entry
RIO packet is dropped and ignored
Bit 0: IER
Bit 0: IER
Yes
Same as previous entry except error capture is done from original request Same as previous entry
--
Bit 8: UR
Bit 8: UR
No
RIO packet is dropped and ignored
Table 10 Hardware Error for Response Transactions
58 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Interrupt Generated if enable bit set on LTLEECSR Bit 4: ITD
Notes
Error
Status Bit set on LTLEDCSR
RIO Error Response Generated
Logical/Transport Layer Capture Register
Comments
Packet Size (All non-maintenance and non-message). Write response - Header size in not 8 Bytes for Small Transport packet or not 12 Bytes for Large Transport packet. PayloadSize IO - Read Response total payload is not of the size requested. Packet response time-out Response is not received by configured time for packets requiring RIO response. Done response is not received in configured time.
Bit 4: ITD
No
Same as previous entry
RIO packet is dropped and ignored
Bit 4: ITD
Bit 4: ITD
No
Same as previous entry
RIO packet is dropped and ignored
Bit 7: PRT
Bit 7: PRT
Yes
Same as previous entry except error capture is done from original request
Interrupt is generated
Table 10 Hardware Error for Response Transactions
59 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet* Errors for Reserved FType
Interrupt Generated if enable bit set on LTLEECSR Bit 4: ITD
Notes
Error
Status Bit set on LTLEDCSR
RIO Error Response Generated
Logical/Transport Layer Capture Register
Comments
FType Priority of maintenance read or write request transaction is 3
Bit 4: ITD
No
Using the incoming RIO packet, for Small Transport type packet; LTLACCSR[XA] = packet bits [78:79], LTLACCSR[A] = packet bits [48:76], LTLDIDCCSR[DIDMSB] = 0's, LTLDIDCCSR[DID] = packet bits [16:23], LTLDIDCCSR[SIDMSB] = 0's, LTLDIDCCSR[SID] = packet bits [24:31], LTLCCCSR[FT] = packet bits [12:15], LTLCCCSR[TT] = packet bits [32:35] For Large Transport type packets; LTLACCSR[XA] = packet bits [94:95], LTLACCSR[A] = packet bits [64:92], LTLDIDCCSR[DIDMSB] = packet bits[16:23], LTLDIDCCSR[DID] = packet bits [24:31], LTLDIDCCSR[SIDMSB] = packet bits[32:39], LTLDIDCCSR[SID] = packet bits [40:47], LTLCCCSR[FT] = packet bits [12:15], LTLCCCSR[TT] = packet bits [48:51]
RIO packet dropped
TransportType Received reserved TT Received TT which is not enabled DestID DestID does not match this port's DeviceID or Alternate DeviceID when enabled
Bit 28: TSE
Bit 28: TSE
No
Same as previous entry
RIO packet is dropped
Bit 5: ITTE
Bit 5: ITTE
Yes
Same as previous entry
--
Table 11 Hardware Errors for Reserved Ftype
60 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
7.4 Other Serial Buffer Errors
All errors that are not covered by the RapidIO Error Management Extension will be handled by the flag registers and the user programmed reporting methods (flag mask) for those flags. It should be noted that some of the sRIO error are also included in the flag registers and may result in reporting by both the RapidIO Error Management, and the normal flag mask.
61 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
62 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
8.0 Registers
The registers of the SerB are grouped into functions. Register types include the following: sRIO Registers (CARs and CSRs) SerB Configuration Registers SerB Error Counter Registers SERDES Control Registers Flag & Flag Mask Registers In the sRIO world, the term CSR is used for "Command and Status Registers". These are the combination of the configuration and flag registers. All registers are accessible by S-Port, I2C and JTAG. Not all parts of the registers are necessarily accessed from all parts. The programming of the configuration registers are described in the section on system initialization. When using sRIO, the configuration registers are accessible only through maintenance packets. They cannot be accessed by using NWRITE, NREAD or SWRITE. As a further grouping, the electrical characteristics of the ports and presence of external memory should remain fixed once configured, so these should be separated from configurations that may change. It is more likely that destination IDs and other soft configurations will change, especially in large applications that are not adequately served by four output queues on a port. The configuration registers are broken into blocks of related functions that may be read by any port and written by any port that will not kill itself in process. It should be noted that in addition to the registers shown here, others exist that are described elsewhere and in the sRIO specification. An example is the Error Management registers that may be found in the RapidIO Part 8: Error Management Extension Specification and in the "Error Handling" section of this document.
8.1 sRIO Registers
This chapter describes the visible register set that allows an external processing element to determine the capabilities, configuration, and status of a processing element using this logical specification. All registers are 32-bits and aligned to a 32-bit boundary. 8.1.1 Register Summary Table below shows the register map for this RapidIO specification. These capability registers (CARs) and command and status registers (CSRs) can be accessed using RapidIO maintenance operations. Any register offsets not defined are considered reserved for this specification unless otherwise stated. Other registers required for a processing element are defined in other applicable RapidIO specifications and by the requirements of the specific device and are beyond the scope of this specification. Read and write accesses to reserved register offsets shall terminate normally and not cause an error condition in the target device. Writes to CAR (read-only) space shall terminate normally and not cause an error condition in the target device. 8.1.2 Extended Features Data Structure The RapidIO capability and command and status registers implement an extended capability data structure. If the extended features bit (bit 28) in the processing element features register is set, the extended features pointer is valid and points to the first entry in the extended features data structure. This pointer is an offset into the standard 16 Mbyte capability register (CAR) and command and status register (CSR) space and is accessed with a maintenance read operation in the same way as when accessing CARs and CSRs. The extended features data structure is a singly linked list of double-word structures. Each of these contains a pointer to the next structure (EF_PTR) and an extended feature type identifier (EF_ID). The end of the list is determined when the next extended feature pointer has a value of logic 0. All pointers and extended features blocks shall index completely into the extended features space of the CSR space, and all shall be aligned to a double-word boundary so the three least significant bits shall equal logic 0. Pointer values not in extended features space or improperly aligned are illegal and shall be treated as the end of the data structure.
63 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
8.1.3 Base Feature Address Space
Block Byte Offset 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 0x80 0x88 0x90 - 0xF8 Reserved Reserved Load Configuration Space Base Address 0 CSR Base Device ID CSR Host Base Device ID Lock CSR Reserved (part 3) Reserved (part 3) Reserved (part 11) Reserved (part 11) Reserved Local Configuration Space Base Address 1 CSR Reserved Component TAG CSR Reserved (part 3) Reserved Reserved (part 11) Reserved Reserved (part 11) Reserved (part 11) Reserved Processing Element Logical Layer CSR Register Name (word 0) Device Identity CAR Assembly Identity CAR Processing Element Features CAR Source Operation CAR Reserved Reserved Reserved (part 3) Reserved Register Name (word 1) Device Information CAR Assembly Information CAR Reserved Destination Operation CAR
Table 12 RIO Base Feature Address Space
8.1.4 Capability Registers The SerB contains a set of Capability Registers (CARs) that allows an external processing element to determine its capabilities through maintenance read operations. All registers are 32 bits wide and are organized and accessed in 32-bit (4 byte) quantities. CARs are read-only and are big-endian with bit 0 the most significant bit. The use of CARs is described in the RIO Input/Output Logical Specification in Chapter 5.
Device Identity CAR
The Device Identity field identifies the vendor that manufactured the device containing the processing element. A value for the Device Identity field is uniquely assigned to a device vendor by the registration authority of the RIO Trade Association. The Device Identity field is intended to uniquely identify the type of device from the vendor specified by the Device Identity field. The values for the Device Identity field are assigned and managed by the respective vendor.
Name:
Bit 15:0 31:16
DEV_ID_CAR
Field Name DEV_VEND_ID DEV_ID
Address:
Reset Value 0x0038 0x04F0
0x00000
Comment
Device Vendor Identifier. Device Identifier.
Table 13 Device ID CAR 64 of 172 March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
Note: 1. The above register is described in the RIO Specification Part 1, sec. 5.4.1
Device Information CAR
The DeviceRev field is intended to identify the revision level of the device. The value for the DeviceRev field is assigned and managed by the vendor specified by the Device Vendor Identity field. DICAR is a read only register.
Name:
Bit 31:0
DEV_INFO_CAR
Field Name DEV_REV
Address:
Reset Value All 0s
0x00004
Comment
Device Revision Level.
Table 14 Device Information CAR
Note: 1. The above register is described in the RIO Specification Part 1, sec. 5.4.2
Assembly Identity CAR
The AssyVendorIdentity field identifies the vendor that manufactured the assembly or subsystem containing the device. A value for the AssyVendorIdentity field is uniquely assigned to a assembly vendor by the registration authority of the RIO Trade Association. The AssyIdentity field is intended to uniquely identify the type of assembly from the vendor specified by the AssyVendorIdentity field. The values for the AssyIdentity field are assigned and managed by the respective vendor. AIDCAR is a read only register.
Name:
Bit 15:0 31:16
ASSY_ID_CAR
Field Name ASSY_VEND_ID ASSY_ID
Address:
Reset Value 0x0000 0x0000
0x00008
Comment
Assembly Vendor Identifier. Assembly Identifier.
Table 15 Assembly ID CAR
Note: 1. The above register is described in the RIO Specification Part 1, sec. 5.4.3
Assembly Information CAR
AICAR contains additional information about the assembly and the pointer to the first entry in the extended features list. AICAR is a read only register.
Name:
Bit 15:0 31:16
ASSY_INFO_CAR
Field Name EXT_FEAT_PTR ASSY_REV
Address:
Reset Value 0x0100 0x0001
0x0000C
Comment
Extended Features Pointer Field: Pointer to the first entry in the extended features list. Assembly Revision Level.
Table 16 Assembly Info CAR
65 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
Note: 1. The above register is described in the RIO Specification Part 1, sec. 5.4.4
Processing Element Features CAR
PEFCAR identifies the major functionality provided by the processing element. PEFCAR is a read only register.
Name:
Bit 2:0
PROC_ELE_FEAT_CAR Address:
Field Name EXT_ADDR_SUP Reset Value 3b001
0x00010
Comment
Extended Addressing Support: Indicates the number of address bits supported by the PE both as a source and target of an operation. 3b001 indicates support for 34 bit addresses.
3
EXT_FEAT
1b1
Extended Features: PE has extended features list; the extended features pointer is valid. Common Transport Large System Support: When enabled it indicates support for 16 bit source and destination ID's.
Critical Request Flow Support: 1b0 - PE does not support CRFS 1b1 - PE supports CRFS SerB does not support CRFS, hence this bit is hard wired to zero. Re-transmit Suppression Support: 1b0 - PE does not support RTSS 1b1 - PE supports RTSS SerB does not support RTSS, hence this bit is hard wired to zero.
4
COM_TRANS_SUP
1b0
5
CRF_SUP
1b0
6
RE_TRNS_SUP
1b0
7
FLO_CNT_SUP
1b0
Flow Control Support: SerB does not support FCS, hence this bit is hard wired to zero. Standard route table configuration support: SerB does not support SRTCS, hence this bit is hard wired to zero. Extended route table configuration support: SerB does not support ERTCS, hence this bit is hard wired to zero. Multicast Extension Support: SerB does not support Multicast, hence this bit is hard wired to zero. Reserved. Indicates that the RIO controller supports inbound doorbells. Mailbox 3:0: Bt 0 indicates PE supports inbound mailbox 0. Bit 1 indicates PE supports inbound mailbox 1. Bit 2 indicates PE supports inbound mailbox 2. Bit 3 indicates PE supports inbound mailbox 3. Reserved. Indicates that the PE can bridge to another external RIO interface. Indicates that the PE physically contains a local processor that executes code. Indicates that the PE has physically addressable local address space and can be accessed as an endpoint through non-maintenance operations. Indicates that the PE can bridge to another interface. Table 17 Process Element Features CAR 66 of 172 March 19, 2007
8
STD_RTCS
1b0
9
EXT_RTCS
1b0
10
MCAST_SUP
1b0
18:11 19 23:20
DOORBELL MAILBOX
0 1b1 4b0
27:24 28 29
SWITCH PROCESSOR
0 1b0 1b0
30
MEMORY
1b1
31
BRIDGE
1b0
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
Note: 1. The above register is described in the RIO Specification Part 1, sec. 5.4.5, Part 3, sec. 3.4.1, Part 6, sec. 6.4.1, Part 9, sec. 4.2, and Part 11, sec. 3.2
Source Operations CAR
SRCOPCAR defines the set of RIO IO logical operations that can be issued by this processing element. SRCOPCAR is a read only register.
Name:
Bit 1:0 2 9:3 10 11 12 13 14 15 31:16 PORT_WR DBELL DATA_MSG NWR_W_RESP STRM_WR NWRITE NREAD -
SRC_OPS_CAR
Field Name 0 1b1 0 1b1 1b0 1b1 1b1 1b1 1b1 0
Address:
Reset Value
0x000018
Comment
Reserved. Port Write: PE support a port-write operation. Reserved Doorbell: PE can support a doorbell operation. Data Message: PE can support a data message operation. NWRITE_R: PE support a Nwrite_R operation. Streaming Write: PE support an Swrite operation. NWRITE: PE support a Nwrite operation. NREAD: PE support a Nread operation. Reserved.
Table 18 Source Operations CAR
Note: 1. The above register is described in the RIO Specification Part 1, sec. 5.4.7, Part 2, sec. 5.4.1, Part 5, sec. 5.4.1, and Part 10, sec. 5.4.1
Destination Operations CAR
DESTOPCAR defines the set of RIO I/O operations that can be supported by this processing element. DESTOPCAR is a read only register.
Name:
Bit 1:0 2 9:3 10 PORT_WR DBELL
DEST_OPS_CAR
Field Name 0 1b0 0 1b1
Address:
Reset Value
0x00001C
Comment
Reserved. Port Write: PE support a port-write operation. Reserved Doorbell: PE can support a doorbell operation.
Table 19 Destination Operations CAR 67 of 172 March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Bit 11 12 13 14 15 31:16 Field Name DATA_MSG NWR_W_RESP STRM_WR NWRITE NREAD Reset Value 1b0 1b1 1b1 1b1 1b1 0 Comment Data Message: PE can support a data message operation. NWRITE_R: PE support a Nwrite_R operation. Streaming Write: PE support an Swrite operation. NWRITE: PE support a Nwrite operation. NREAD: PE support a Nread operation. Reserved.
Notes
Table 19 Destination Operations CAR
Note: 1. The above register is described in the RIO Specification Part 1, sec. 5.4.8, Part 2, sec. 5.4.2, Part 5, sec. 5.4.2, Part 10, sec. 5.4.2
8.1.5 Command and Status Registers The SerB contains a set of Command and Status Registers (CSRs) that allows an external processing element to control and determine the status of its internal hardware. All registers are 32 bits wide and are organized and accessed in the same way as the CARs. Refer to Table 5-2 of the RIO Input/Output Logical Specification in Chapter 5 for the required behavior for accesses to reserved registers and register bits.
Processing Element Logical Layer Control CSR
PELLCCSR controls the extended addressing abilities. SerB will only support 34-bit addressing. PELLCCSR is a read only register.
Name:
Bit 2:0
PROC_ELMT_CTRL_CSRAddress:
Field Name EXT_ADDR_CTRL Reset Value 3b001
0x00004C
Comment
Extended Addressing Control (read-only): Controls the number of address bits generated by the PE as a source and processed by the PE as the target of an operation. 3b100 - PE supports 66 bit addresses 3b010 - PE supports 50 bit addresses 3b001 - PE supports 34 bit addresses (default) All other encoding reserved. Reserved.
31:3
-
0
Table 20 Processing Element Logical Layer Control CSR
Note: 1. The above register is described in the RIO Specification Part 1, sec. 5.5.1
Local Configuration Space Base Address 1 CSR
The local configuration space base address 1 command and status register specifies the least significant bits of the local physical address double-word offset for the processing element's configuration register space, allowing the configuration register space to be physically mapped in the processing element. This register allows configuration and maintenance
68 of 172
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IDT 80KSBR200
Advanced Datasheet*
Notes
of a processing element through regular read and write operations rather than maintenance operations. The double-word offset is right-justified in the register. As is the case with all registers, an external processor writing to LCSBA1CSR should not assume it has been written until a response has been received.
Name:
Bit 16:0 30:17 LCL_BASE_ADDR
LCL_CONF_ADDR_1_CSRAddress: 0x00005C
Field Name 0 0x 0000 Reset Value Reserved. Local Configuration Space Base Address: These bits correspond to the highest 14 bits of the 34-bit RIO address space. Reserved. Comment
31
-
0
Table 21 Local Configuration Space Base Address 1 CSR
Note: 1. The above register is described in the RIO Specification Part 1, sec. 5.5.3
Base Device ID CSR
The sRIO searchable source and destination IDs are contained in the Base Device ID CSR, and are programmed by sRIO according to the sRIO specification. There are locations for both 8 and 16 bit device IDs as described in the RapidIO, Part 3, Common Transport Specification in section 3.5.1. The SerB shall allow programming of both, in order to allow both 8 and 16 bit operations simultaneously. Both device IDs may be read by any of the interfaces with access to the configuration registers. The device IDs are cleared only by Master Reset or by a specific write to the Base Device ID CSR. Other resets, such as Load Configuration will have no affect on the Base Device ID CSR. The Base Device ID CSR has no shadow register. Note: This register is in the sRIO spec and that spec overrides this info.
Name:
Bit 16:0
BASE_DEV_ID_CSR
Field Name LRG_BASE_DEVID
Address:
Reset Value 0xFFFF
0x000060
Comment
Large Base Device ID: SerB Source/Destination ID is 16 bits. The Base ID of the device in a large common transport system. This field is valid only if bit 27 of the Processing Element Features CAR is set. Base Device ID: SerB Source/Destination ID is 8 bits. The Base ID of the device in a small common transport system (RIO device ID) Reserved.
30:17
BASE_DEVID
0xFF
31
-
0
Table 22 Base Device ID CSR
Note: 1. The above register is described in the RIO Specification Part 3, sec. 3.5.1
Host Base Device ID Lock CSR
The host base device ID lock CSR contains the base device ID value for the processing element in the system that is responsible for initializing this processing element. The HBDID field is a write-once/resettable field which provides a lock function. Once the HBDID field is written, all subsequent writes to the field are ignored, except in the case that the value written matches the value contained in the field. In this case, the register is re-initialized to 0xFFFF. After writing the HBDID field, a processing element must then read the host base device ID lock CSR to verify that it owns the lock before attempting to initialize this processing element.
69 of 172 March 19, 2007
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IDT 80KSBR200
Advanced Datasheet* Name:
Bit 15:0
Notes
HOST_BASE_DEV_LOCK_CSRAddress:0x000068
Field Name HOST_BASE_DID Reset Value 0xFFFF Comment Host Base Device ID: This is the host base device ID for the processing element that is responsible for initializing this device. Only the first write to this field is accepted, all other writes are ignored, except in the case that the value written matches the value contained in the field. In this case, the register is re-written to 0xFFFF. Reserved.
31:16
-
0
Table 23 Host Base Device ID Lock CSR
Note: 1. The above register is described in the RIO Specification Part 3, sec. 3.5.2
Component Tag CSR
The component tag CSR contains a component tag value for the processing element and can be assigned by software when the device is initialized. It is unused internally in SerB. It is especially useful for labeling and identifying devices that are not end points and do not have device ID registers.
Name:
Bit 31:0
COMP_TAG_CSR
Field Name COMP_TAG
Address:
Reset Value All 0s
0x00006C
Comment
Component Tag: This is a component tag for the PE.
Table 24 Component Tag CSR
Note: 1. The above register is described in the RIO Specification Part 3, sec. 3.5.3
70 of 172
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IDT 80KSBR200
Advanced Datasheet*
Notes
8.1.6 Extended Features Register Summary Table below shows the Extended Features register map for this RapidIO specification. These capability registers (CARs) and command and status registers (CSRs) can be accessed using RapidIO maintenance operations. There are four types of 1x/4x LP-Serial devices, as an end point device. SerB supports an end point device with additional software recovery registers. 8.1.7 Extended Features Address Space
Block Byte Offset 0x100 0x108 0x110 0x118 0x120 0x128 0x130 0x138 0x140 0x148 0x150 0x158 0x160 - 0x178 0x180 - 0x198 0x1A0 - 0x1B8 0x1C0 - 0x538 0x600 0x608 0x610 0x618 0x620 0x628 0x630 - 0x638 0x640 0x648 0x650 0x658 0x660 0x668 0x680 - 0x6B8 0x6C0 - 0x6F8 0x700 - 0x738 0x740 - 0xE38 Port 0 Error Rate CSR Port 0 Error Detect CSR Port 0 Attributes Capture CSR Port 0 Packet Capture 1 CSR Port 0 Packet Capture 3 CSR Reserved Port 0 Error Rate Threshold CSR Reserved for Port 1 Registers Reserved for Port 2 Registers Reserved for Port 3 Registers Reserved for Port 4 through 15 Registers Port-write Target deviceID CSR Reserved Port 0 Error Rate Enable CSR Port 0 Packet/Control Symbol Capture 0 CSR Port 0 Packet Capture 2 CSR Reserved Port 0 Error and Status CSR Reserved for Port 1 Registers Reserved for Port 2 Registers Reserved for Port 3 Registers Reserved for Port 4 through 15 Registers Error Management Extensions Block Header Logical/Transport Layer Error Detect CSR Logical/Transport Layer High Address Capture CSR Logical/Transport Layer Device ID Capture CSR Reserved Logical/Transport Layer Error Enable CSR Logical/Transport Layer Address Capture CSR Logical/Transport Layer Control Capture CSR Reserved Port 0 Link Maintenance Request CSR Port 0 Local ackID Status CSR Reserved Port 0 Control CSR Port Link Time-Out Control CSR Reserved Reserved Port General Control CSR Port 0 Link Maintenance Response CSR Reserved Register Name (word 0) 1x/4x LP-Serial Register Block Header Reserved Reserved Reserved Port Response Time-Out Control CSR Register Name (word 1) Reserved
Reserved Packet Time-to-live CSR
Table 25 RIO Extended Features Address Space
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IDT 80KSBR200
Advanced Datasheet* 1x/4x LP-Serial Register Block Header
Notes
The port maintenance block header 0 register contains the EF_PTR to the next EF_BLK (Extended Features Space, Error Management) and the EF_ID that identifies this as the generic end point port maintenance block header. Note that while registers defined by software assisted error recovery are supported, software assisted error recovery is not (these registers are included for hot insertion only); therefore, RIO is defined here as not supporting software assisted error recovery. PMBH0CSR is a read-only register.
Name:
Bit 15:0 31:16
PORT_MAINT_BLK_HDRAddress:
Field Name EF_ID EF_PTR Reset Value 0x0001 0x0600
0x000100
Comment
Extended Features ID: Hard wired extended features ID, Generic End Point Devices. Extended Features Pointer: Hard wired pointer to the next block in the data structure.
Table 26 1x/4x LP-Serial Register Block Header
Note: 1. The above register is described in the RIO Specification Part 6, sec. 6.6.2.1
Port Link Time-out Control CSR
The port link time-out control register contains the time-out timer value for all ports on a device. This time-out is for link events such as sending a packet to receiving the corresponding acknowledge and sending a link-request to receiving the corresponding link-response. The reset value is the maximum time-out interval, and represents between 3 and 5 seconds.
Name:
Bit 7:0 31:8 PORT_LINK_VAL
PORT_LNK_TO_CTRL_CSRAddress: 0x000120
Field Name 0 0xFFFFFF Reset Value Reserved. Port Link Time-out Internal Value: Setting to all 0's disables the link time-out timer. This value is loaded each time the link time-out timer starts. Comment
Table 27 Port Link Time-out CSR
Note: 1. The above register is described in the RIO Specification Part 6, sec. 6.6.2.2
Port Response Time-out Control CSR
The port response time-out control register contains the time-out timer count for all ports on a device. This time-out is for sending a request packet to receiving the corresponding response packet. The reset value is the maximum time-out interval, and represents between 3 and 5 seconds.
Name:
Bit 7:0 31:8 PORT_RESP_VAL
PORT_RESP_TO_CTRL_CSRAddress:0x000124
Field Name 0 0xFFFFFF Reset Value Reserved. Port Response Time-out Internal Value: Setting to all 0's disables the link time-out timer. This value is loaded each time the link time-out timer starts. Comment
Table 28 Port Response Time-out CSR 72 of 172 March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
Note: 1. The above register is described in the RIO Specification Part 6, sec. 6.6.2.3
Port General Control CSR
The port general control register contains control register bits applicable to all ports on a processing element.
Name:
Bit 28:0 29 DISCOVER
PORT_GEN_CTRL_CSR Address:
Field Name 0 1b0 Reset Value
0x00013C
Comment
Reserved. Discovered: This device has been located by the processing element responsible for system configuration. 0b0 - The device has not been previously discovered. 0b1 - The device has been discovered by another processing element. Master Enable: The master enable bit controls whether or not a device is allowed to issue requests into the system. If the Master Enable is not set, the device may only respond to requests. 0b0 - processing element cannot issue requests. 0b1 - processing element can issue requests. Host: A host device is a device that is responsible for system exploration, initialization, and maintenance. Agent or slave devices are typically initialized by Host devices. 0b0 - agent or slave device. 0b1 - host device.
30
MSTR_EN
1b0
31
HOST
1b0
Table 29 Port General Control CSR
Note: 1. The above register is described in the RIO Specification Part 6, sec. 6.6.2.4
Port 0 Link Maintenance Request CSR
The port 0 link maintenance request register is accessible both by a local processor and an external device. A write to this register generates a link-request control symbol on the corresponding RIO port interface. Care should be taken when writing this register that it is only used for hot swap and not for software assisted error recovery (which is not supported).
Name:
Bit 2:0
P0_LNK_MAINT_REQ_CSRAddress: 0x000140
Field Name CMD Reset Value 3b000 Comment Command: LINK_REQUEST command to send. If read, this field returns the last written value. If written with a value other than 3b011 (reset-device) or 3b100 (input-status), resulting operation will be undefined, as all other values are reserved in the RIO spec. Reserved.
31:3
-
0
Table 30 Port 0 Link Maintenance Request CSR
Note: 1. The above register is described in the RIO Specification Part 6, sec. 6.6.2.5
73 of 172
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IDT 80KSBR200
Advanced Datasheet* Port 0 Link Maintenance Response CSR
Notes
The port 0 link maintenance response register is accessible both by a local processor and an external device. A read to this register returns the status received in a link-response control symbol. This register is read-only.
Name:
Bit 4:0 9:5 30:10 31
P0_LNK_MAINT_RES_CSRAddress: 0x000144
Field Name LNKS ACKS RVLD Reset Value 0x00 0x00 0 1b0 Comment Link Status: link status field from the link-response control symbol. ackID Status: ackID status field from the link-response control symbol. Reserved. Response Valid: If the link-request causes a link-response, this bit indicates that the link-response has been received and the status fields are valid. If the link-request does not cause a link-response, this bit indicates that the link-request has been transmitted. This bit automatically clears on read.
Table 31 Port 0 Link Maintenance Response CSR
Note: 1. The above register is described in the RIO Specification Part 6, sec. 6.6.2.6
Port 0 Local ackID Status CSR
The port n local ackID status register is accessible both by a local processor and an external device. A read to this register returns the local ackID status for both the output and input ports of the device. Care should be taken to use this register only for hot swap and not software error management.
Name:
Bit 4:0
P0_LOC_ACK_STAT_CSRAddress:
Field Name OBACKID Reset Value 0x00
0x000148
Comment
Outbound Ack ID: This can be written by software but only if there are no outstanding unacknowledged packets. If there are, a newly-written value will be ignored. Reserved. Outstanding port unacknowledge ackID status: Next expected acknowledge control symbol ackID field that indicates the ackID value expected in the next received acknowledge control symbol. Note that this value is read-only even though RIO spec allows for it to be writable. Reserved. Inbound ackID: Input port next expected ackID value. Reserved.
7:5 12:8
OACKID
0 0x00
23:13 28:24 31:29
IACKID -
0 0x00 0
Table 32 Port 0 Local ackID Status CSR
Note: 1. The above register is described in the RIO Specification Part 6, sec. 6.6.2.7
74 of 172
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IDT 80KSBR200
Advanced Datasheet* Port 0 Error and Status CSR
Notes
This register is accessed when a local processor or an external device wishes to examine the port error and status information.
Name:
Bit 0
P0_ERR_STAT_CSR
Field Name PORT_UNINIT
Address:
Reset Value 1b1
0x000158
Comment
Port Uninitialized: Input and output ports are not initialized. This bit and bit 30 are mutually exclusive (read-only). Port OK: The input and output ports are initialized and the port is exchanging error-free control symbols with the attached device (read-only). Port Error: Input or output port has encountered an error from which hardware was unable to recover. Once set, remains set until written with a logic 1 to clear. Reserved. Port-write Pending: Port has encountered a condition which required it to initiate a Maintenance Port-write operation. This bit is only valid if the device is capable of issuing a maintenance port-write transaction. Once set, remains set until written with a logic 1 to clear. Reserved. Input Error-stopped: Input port is stopped due to transmission error (read-only). Input Error-encountered: Input port has encountered (and possibly recovered from) a transmission error. This bit is set when bit 23 is set. Once set, remains set until written with a logic 1 to clear. Input Retry-stopped: Input port is stopped due to a retry (read-only). Reserved. Output Error-stopped: Output port is stopped due to a transmission error (read-only). Output Error-encountered: Output port has encountered (and possibly recovered from) a transmission error. This bit is set when bit 15 is set. Once set, remains set until written with a logic 1 to clear. Output Retry-stopped: Output port is stopped due to a retry (read-only). Output Retried: Output port has received a packet-retry control symbol and can not make forward progress. This bit is set when bit 13 is set and cleared when a packet-accepted or packet-not-accepted control symbol is received (read-only). Output Retry-encountered: Output port has encountered a retry condition. This bit is set when bit 13 is set. Once set, remains set until written with a logic 1 to clear. Reserved.
1
PORT_OK
1b0
2
PORT_ERR
1b0
3 4
PORT_WR_PEND
0 1b0
7:5 8 9
IN_ERR_STOP IN_ERR_ENC
0 1b0 1b0
10 15:11 16 17
IN_RTRY_STOP OUT_ERR_STOP OUT_ERR_ENC
1b0 0 1b0 1b0
18 19
OUT_RTRY_STOP OUT_RETRY
1b0 1b0
20
OUT_RTRY_ENC
1b0
23:21
-
0
Table 33 Port 0 Error and Status CSR 75 of 172 March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Bit 24 Field Name OUT_DGRD_ENC Reset Value 1b0 Comment Output Degraded-encountered: Output port has encountered a degraded condition, meaning that the Error Rate Counter has met or exceeded the port's degraded error threshold. Once set remains set until written with a logic 1 to clear. Once cleared, will not assert again unless the Error Rate Counter dips below the port's degraded error threshold and then meets or exceeds it again. Output Failed-encountered: Output port has encountered a failed condition, meaning that the Error Rate Counter has met or exceeded the port's failed error threshold. Once set, remains set until written with a logic 1 to clear. Once cleared, will not assert again unless the Error Rate Counter dips below the port's failed error threshold and then meets or exceeds it again. Output Packet-dropped: Output port has discarded a packet. A packet will be discarded if: 1. it is received while OFE is set and drop packet enable is set and stop on port failed is set. 2. it is received while output buffer drain enable is set. 2. it is not-accepted by the link-partner while error rate failed threshold trigger is met or exceeded and link-response returns expected ackID. Once set, it remains set until written with a logic 1 to clear. Reserved.
Notes
25
OUT_FAIL_ENC
1b0
26
OUT_PKT_DROP
1b0
31:27
-
0
Table 33 Port 0 Error and Status CSR
Note: 1. The above register is described in the RIO Specification Part 6, sec. 6.6.2.8
Port 0 Control CSR
The port 0 control register contains control register bits for the individual port on a processing element.
Name:
Bit 0
P0_CTRL_CSR
Field Name PORT_TYPE
Address:
Reset Value 1b0
0x000158
Comment
Port Type, this indicates the port type (read-only): 1b0 - Port receiver/drivers are enabled 1b1 - Port receivers/drivers are disabled and are unable to receive/ transmit any packets or control symbols Port Lockout: 1b0 - The packets that may be received and issued are controlled by the state of the OPE and IPE bits. 1b1 - This port is stopped and is not enabled to issue or receive any packets. Drop Packet Enable: This bit is used with the Stop on Port Failed-encountered Enable bit to force certain behavior when the Error Rate Failed Threshold has been met or exceeded. Stop on Port Failed-encountered Enable: This bit is used with the Drop Packet Enable bit to force certain behavior when the Error Rate Threshold has been met or excessed.
1
PORT_LOCK
1b0
2
DROP_PKT_EN
1b0
3
STOP_PORT_FAIL
1b0
Table 34 Port 0 Control CSR 76 of 172 March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Bit 11:4 Field Name RE_XMT_MASK Reset Value 0x00 Comment Re-transmit Suppression Mask: Suppress packet re-transmission on CRC error. SerB does not support this feature and these bits are set to zero. Reserved. Enumeration Boundary: An enumeration boundary aware system enumeration algorithm shall honor this flag. The algorithm, on either the ingress or the egress port, shall not enumerate past a port with this bit set. This provides for software enforced enumeration domains within the RIO fabric. Flow Control Participant, enable flow control transactions: 1b0 - Do not route or issue flow control transactions to this port 1b1 - Route or issue flow control transactions to this port. (RIO spec. Part 9, sec. 4.3) Multicast-event Participant: This bit is hard-wired to 0. Error Checking Disable, this bit disables all RIO transmission error checking: 1b0 - error checking and recovery is enabled 1b1 - error checking and recovery is disabled Input Port Enable, input port receive enable: 0b0 - port is stopped and only enabled to route or respond to I/O logical MAINTENANCE packets. 0b1 - port is enabled to respond to any packet. Output Port Enable, output port transmit enable: 1b0 - port is stopped and not enabled to issue any packets except to route or respond to I/O Logical Maintenance packets. 1b1 - port is enabled to issue any packets. Port Disable: 1b0 - Port receiver/drivers are enabled 1b1 - Port receivers/drivers are disabled and are unable to receive/ transmit any packets or control symbols Port Width Override, soft port configuration to override the hardware size: 3b000 No override 3b001 Reserved 3b010 Force single lane, lane 0 3b011 Force single lane, lane 2 3b100 - 3b111 Reserved The change of this field during normal mode may cause re-initialization. Initialized Port Width, width of the ports after initialized (read-only): 3b000 Single-lane port, lane 0 3b001 Single-lane port, lane 2 3b010 Four-lane port 3b011 - 3b111 Reserved. Port Width, hardware width of the port (read-only): 2b00 Single-lane port 2b01 Four-lane port 2b10 - 2b11 Reserved.
Notes
16:12 17
ENUM_BOUN
0 1b0
18
FLO_CTRL_PART
1b0
19
MULTI_PART
1b0
20
ERR_CHK_DIS
1b0
21
IN_PORT_EN
1b0
22
OUT_PORT_EN
1b0
23
PORT_DIS
1b0
26:24
PORT_OVER
3b000
29:27
INIT_PORT_WDTH
HW
31:30
PORT_WIDTH
HW
Table 34 Port 0 Control CSR
Note: 1. The above register is described in the RIO Specification Part 6, sec. 6.6.2.9
77 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
8.1.8 Error Management Extensions Summary
Error Management Extensions Block Header
The error management extensions block header register contains the EF_PTR to the next EF_BLK and the EF_ID that identifies this as the error management extensions block header.
Name:
Bit 15:0 31:16
ERR_MGMT_BLK_HDR Address:
Field Name EXT_FEAT_ID EXT_FEAT_PTR Reset Value 0x0007 0x0000
0x000600
Comment
Extended Features ID: Hard wired extended features ID. Extended Features Pointer: Hard wired pointer to the next block in the data structure.
Table 35 Error Management Extensions Block Header
Note: The above register is described in the RIO Specification Part 8, sec. 2.3.2.1
Logical/Transport Layer Error Detect CSR
This register indicates the error detected by the Logical or Transport logic layer. Multiple bits may get set in the register if simultaneous errors are detected during the same clock cycle that the errors are logged, or if the detected errors are not enabled for capture. LTLEDCSR is stored in each GRIO port and the Message Unit, although the values in this register can differ for each port/Message Unit. A port's LTLEDCSR cannot detect any errors if the port or the Message Unit has captured an enabled Logical/Transport layer error until the detected error is cleared, and likewise, the Message Unit's LTLEDCSR cannot detect any errors if the Message Unit or any port has captured an enabled Logical/Transport layer error. Software should write this register with all 0's to clear the detected error and unlock the capture registers in all ports/ Message Unit. Undefined results will occur if this register is written or read while actual Logical/Transport Layer errors are being detected by the port (where detect cannot occur if an error has already been detected and not yet cleared). If a port detects multiple errors in the same cycle, multiple LTLEDCSR bits will be set to reflect this. If one or all of these bits are enabled, capture is done on a priority basis. If PRT is set and enabled, and multiple bits are detected in LTLEDCSR, the capture information corresponds to PRT. If PRT is not set or not enabled, then all set and enabled LTLEDCSR bits correspond to the captured packet. If more than one port or Message Unit detects one or more enabled errors in the same cycle, the capture registers will be saved in the top port /Message Unit in the PBUS daisy chain that detected an enabled error, and the set and enabled detect bits of the port(s)/Message Unit below will be masked from the PBUS daisy chain. This means that a read of LTLEDCSR will only return the un-enabled set bits from any port/Message Unit and enabled set bits from the top port / Message Unit in the daisy chain with a set enabled error, and that a read of the capture registers will return the values in the top port /Message Unit in the daisy chain with a set enabled error; i.e., the set enabled detect bits will correspond to the capture registers.
Name:
Bit 2:0 3 TRSP_SZE_ERR
LTL_ERR_DET_CSR
Field Name 0 1b0
Address:
Reset Value
0x000608
Comment
Reserved. Transport Size Error: The tt field is nor consistent with bit 27 of the Processing Element Features CAR (i.e., the tt value is reserved or indicates a common transport system that is unsupported by this device).
Table 36 Logical/Transport Layer Error Detect CSR
78 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Bit 4 21:5 22 Field Name RTRY_TRES_EXC UNSUP_TRANS Reset Value 1b0 0 1b0 Comment Retry Error Threshold Exceeded: The allowed number of logical retries has been exceeded. Reserved. Unsupported Transaction: A transaction is received that is not supported in the Destination Operation CAR (IO/MSG/GSM logical). Unsolicited Response: An unsolicited/unexpected Response packet was received (IO/MSG/ GSM logical). Packet Response Time-out: A required response has not been received within the specified timeout interval (IO/MSG/GSM logical). Message Request Time-out: A required message request has not been received within the specified time-out interval (MSG logical). Illegal Transaction Target Error: Received a packet that contained a destination ID that is not defined for this end point. Illegal Transaction Decode: Received illegal fields in the request/response packet for a supported transaction (IO/MSG/GSM logical). Message Format Error: Received MESSAGE packet data payload with an invalid size or segment (MSG logical). GSM Error Response: Received a response of `ERROR' for a GSM Logical Layer Request. Message Error Response: Received a response of `ERROR' for an MSG Logical Layer Request. IO Error Response: Received a response of `ERROR' for an IO Logical Layer Request.
Notes
23
UNSOL_RES
1b0
24
PKT_RES_TOUT
1b0
25
MSG_REQ_TOUT
1b0
26
ILL_TRANS_ERR
1b0
27
ILL_TRANS_DEC
1b0
28
MSG_FMT_ERR
1b0
29 30
GSM_ERR_RES MSG_ERR_RES
1b0 1b0
31
IO_ERR_RES
1b0
Table 36 Logical/Transport Layer Error Detect CSR
Note: 1. The above register is described in the RIO Specification Part 8, sec. 2.3.2.2
Logical/Transport Layer Error Enable CSR
This register contains the bits that control if an error condition locks the Logical/Transport Layer Error Detect and Capture registers and is reported to the system host. LTLEECSR is stored in all ports and the Message Unit
Name:
Bit 2:0 3 TRAN_SZE_EN
LTL_ERR_EN_CSR
Field Name 0 1b0
Address:
Reset Value
0x00060C
Comment
Reserved. Transport Size Error Enable: Enable error reporting when the tt field is nor consistent with bit 27 of the Processing Element Features CAR (i.e., the tt value is reserved or indicates a common transport system that is unsupported by this device).
Table 37 Logical/Transport Layer Error Enable CSR 79 of 172 March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Bit 4 Field Name RE_TRS_EXC_EN Reset Value 1b0 Comment Retry Error Threshold Exceeded Enable: Enable error reporting when all allowed number of logical retries has been exceeded. Reserved. Unsupported Transaction Error Enable: Enable reporting of an unsupported transaction error. Save and lock transaction capture information in Logical/Transport Layer Device ID and Control Capture CSRs. Unsolicited Response Error Enable: Enable reporting of an unsolicited response error. Save and lock transaction capture information in Logical/Transport Layer Device ID and Control Capture CSRs. Packet Response Time-out Error Enable: Enable reporting of a packet response time-out error. Save and lock original request address in Logical/Transport Layer Address Capture CSRs. Save and lock original request Destination ID in Logical/ Transport Layer Device ID Capture CSRs. Message Request Time-out Enable: Enable reporting of a Message Request time-out error. Save and lock transaction capture information in Logical/Transport Layer Device ID and Control Capture CSRs for the last Message request segment packet received. Illegal Transaction Target Error Enable: Enable reporting of an illegal transaction target error. Save and lock transaction capture information in Logical/Transport Layer Device ID and Control Capture CSRs. Illegal Transaction Decode Enable: Enable reporting of an illegal transaction decode error. Save and lock transaction capture information in Logical/Transport Layer Device ID and Control Capture CSRs. Message Format Error Enable: Enable reporting of a message format error. Save and lock transaction capture information in Logical/Transport Layer Device ID and Control Capture CSRs. GSM Error Response Enable: Enable reporting of a GSM error response. Save and lock original request transaction information in all Logical/Transport Layer Capture CSRs. Message Error Response Enable: Enable reporting of a Message error response. Save and lock original request transaction information in all Logical/Transport Layer Capture CSRs. IO Error Response Enable: Enable reporting of an IO error response. Save and lock original request transaction information in all Logical/Transport Layer Capture CSRs.
Notes
21:5 22
UNS_TRANS_EN
0 1b0
23
UNS_RES_EN
1b0
24
PKT_RES_TO_EN
1b0
25
MSG_REQ_TO_EN
1b0
26
ILL_TRGT_EN
1b0
27
ILL_DEC_EN
1b0
28
MSG_FRMT_EN
1b0
29
GSM_ERR_EN
1b0
30
MSG_ERR_EN
1b0
31
IO_ERR_EN
1b0
Table 37 Logical/Transport Layer Error Enable CSR
Note: 1. The above register is described in the RIO Specification Part 8, sec. 2.3.2.3
80 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet* Logical/Transport Layer Address Capture CSR
Notes
This register contains error information. It is locked when a Logical/Transport error is detected and the corresponding enable bit is set. LTLACCSR is stored in each port and the Message Unit, although the values in this register can differ between each port and Message Unit. The Message Unit LTLACCSR cannot lock if any port has locked; no port LTLACCSR can lock if the Message Unit or any other port has locked. Undefined results will occur if this register is written while actual Logical/Transport Layer errors are being detected by the port.
Name:
Bit 1:0
LTL_ADDR_CAP_CSR
Field Name EXTA
Address:
Reset Value
0x000614
Comment
2b00
xamsbs: Extended address bits of the address associated with the error (for requests, for responses if available). Reserved. address[32:60]: Least significant 29 bits of the address associated with the error (for requests, for responses if available).
2 31:3
ADDR
0 All 0s
Table 38 Logical/Transport Layer Address Capture CSR
Note: 1. The above register is described in the RIO Specification Part 8, sec. 2.3.2.5
Logical/Transport Layer Device ID Capture CSR
This register contains error information. It is locked when a Logical/Transport error is detected and the corresponding enable bit is set. LTLDIDCSR is stored in each port and the Message Unit, although the values in this register can differ between each port and Message Unit. The Message Unit LTLDIDCSR cannot lock if any port has locked; no port LTLDIDCSR can lock if the Message Unit or any other port has locked. Undefined results will occur if this register is written while actual Logical/Transport Layer errors are being detected by the port.
Name:
Bit 7:0
LTL_DEV_ID_CSR
Field Name SRC_ID
Address:
Reset Value 0x00
0x000618
Comment
Source ID: The sourceID (or least significant byte of the source ID if large transport system) associated with the error.
15:8
MSB_SRC_ID
0x00
MSB Source ID: The most significant byte of the sourceID associated with the error. This field is valid only if bit 27 of the Processing Element Features CAR is set (large transport systems only).
23:16
DST_ID
0x00
Destination ID: The destinationID (or least significant byte of the destination ID if large transport system) associated with the error. MSB Destination ID: The most significant byte of the destinationID associated with the error. This field is valid only if bit 27 of the Processing Element Features CAR is set (large transport systems only).
31:24
MSB_DST_ID
0x00
Table 39 Logical/Transport Layer Device ID Capture CSR
Note: 1. The above register is described in the RIO Specification Part 8, sec. 2.3.2.6
81 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet* Logical/Transport Layer Control Capture CSR
Notes
This register contains error information. LTLCCCSR is stored in each port and the Message Unit, although the values in this register can differ between each port and Message Unit. The Message Unit LTLCCCSR cannot lock if any port has locked; no port LTLCCCSR can lock if the Message Unit or any other port has locked. Undefined results will occur if this register is written while actual Logical/Transport Layer errors are being detected by the port.
Name:
Bit 15:0 23:16 MSG_INFO
LTL_CTRL_CAP_CSR
Field Name 0 0x00
Address:
Reset Value
0x00061C
Comment
Reserved. Message Information: Letter, mbox, and message for the last Message request received for the mailbox that had an error (Message errors only). Transaction Type: Transaction type associated with the error.
27:24 31:28
TRANS_TYPE FORMAT_TYPE
0x0 0x0
Format Type: Format type associated with the error.
Table 40 Logical/Transport Layer Control Capture CSR
Note: 1. The above register is described in the RIO Specification Part 8, sec. 2.3.2.7
Port-write Target deviceID CSR
This register contains the target device ID to be used when a device generates a Maintenance port-write operation to report errors to a system host.
Name:
Bit 14:0 15 LRG_TRANS
PORT_WR_TID_CSR
Field Name 0 1b0
Address:
Reset Value
0x000628
Comment
Reserved. Large Transport: DeviceID size to use for a port-write 1b0 - use the small transport deviceID 1b1 - use the large transport deviceID.
23:16 31:24
DEV_ID DEV_ID_MSB
0x00 0x00
DeviceID: This is the port-write target deviceID. DeviceID MSB: This is the most significant byte of the port-write target deviceID (large transport systems only).
Table 41 Port-write Target deviceID CSR
Note: 1. The above register is described in the RIO Specification Part 8, sec. 2.3.2.8
Port 0 Error Detect CSR
The Port 0 Error Detect Register indicates transmission errors that are detected by the hardware. Software can write bits in this register with "1" to cause the Error Rate Counter to increment. Undefined results will occur if this register is written while actual physical layer errors are being detected by the port.
82 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet* Name:
Bit 0
Notes
P0_ERR_DET_CSR
Field Name LINK_TOUT
Address:
Reset Value 1b0
0x000640
Comment
Link Time-out: An acknowledge or link-response control symbol is not received within the specified time-out interval. Unsolicited Acknowledge Control Symbol: An unexpected acknowledge control symbol was received. Delineation Error: Received unaligned /SC/ or /PD/ or undefined code-group. Reserved. Protocol Error: An unexpected packet or control symbol was received. Non-outstanding ackID: Link-response received with an ackID that is not outstanding. Reserved. Received Packet Exceeds 276 Bytes: Received packet which exceeds the maximum allowed size. Received Packet with bad CRC: Received packet with a bad CRC value. Received Packet with Unexpected ackID: Received packet with unexpected ackID value (out-of-sequence ackID).
1 2 3 4 5 16:6 17 18 19
UNS_CTRL_SYM DELIN_ERR PROTO_ERR NOUT_ACKID RCV_PKT_EXC RCV_BAD_CRC RCV_PKT_UACK
1b0 1b0 0 1b0 1b0 0 1b0 1b0 1b0
20 21
RCV_PKT_NCTRL RCV_ACK_SYM
1b0 1b0
Received Packet-not-accepted Control Symbol: Received packet-not-accepted acknowledge control symbol. Received Acknowledge Control Symbol with Unexpected ackID: Received acknowledge control symbol with unexpected ackID (packet-accepted or packet-retry). Received Corrupt Control Symbol: Received a control symbol with a bad CRC value. Reserved.
22 31:23
RCV_CC_SYM -
1b0 0
Table 42 Port 0 Error Detect CSR
Note: 1. The above register is described in the RIO Specification Part 8, sec. 2.3.2.10
Port 0 Error Rate Enable CSR
This register contains the bits that control when an error condition is allowed to increment the error rate counter in the Port 0 Error Rate Threshold Register and lock the Port 0 Error Capture registers.
Name:
Bit 0
P0_ERR_RATE_EN_CSR Address:
Field Name LINK_TOUT_EN Reset Value 1b0
0x000644
Comment
Link Time-out Enable: Enable error rate counting of link time-out errors.
Table 43 Port 0 Error Rate Enable CSR
83 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Bit 1 Field Name UNS_ACK_SYM_E N Reset Value 1b0 Comment Unsolicited Acknowledge Control Symbol Enable: Enable error rate counting of unsolicited acknowledge control symbol errors. Delineation Error Enable: Enable error rate counting of delineation errors. Reserved. Protocol Error Enable: Enable error rate counting of protocol errors. Non-outstanding ackID Enable: Enable error rate counting of link-response received with an ackID that is not outstanding. 16:6 17 RCV_PKT_EXC_E N 0 1b0 Reserved. Received Packet Exceeds 276 Bytes: Enable error rate counting of packet which exceeds the maximum allowed size. Received Packet with bad CRC Enable: Enable error rate counting of packet with a bad CRC value. Received Packet with Unexpected ackID Enable: Enable error rate counting of packet with unexpected ackID value (out-of-sequence ackID). Received Packet-not-accepted Control Symbol Enable: Enable error rate counting of received packet-not-accepted control symbols. Received Acknowledge Control Symbol with Unexpected ackID Enable: Enable error rate counting of an acknowledge control symbol with an unexpected ackID. Received Corrupt Control Symbol Enable: Enable error rate counting of a corrupt control symbol. 31:23 0 Reserved.
Notes
2 3 4 5
DELIN_ERR_EN PROTO_ERR_EN NOUT_ACKID_EN
1b0 0 1b0 1b0
18 19
RCV_BAD_CRC_E N RCV_PKT_ACK_E N
1b0 1b0
20
RCV_PKT_SYM_E N RCV_ACK_SYM_E N
1b0
21
1b0
22
RCV_CC_SYM_EN
1b0
Table 43 Port 0 Error Rate Enable CSR
Note: 1. The above register is described in the RIO Specification Part 8, sec. 2.3.2.11
Port 0 Attribute Capture CSR
The error capture attribute register indicates the type of information contained in the port n error capture registers. In the case of multiple detected errors during the same clock cycle one of the errors must be reflected in the Error type field. The error that is reflected is implementation dependent. Undefined results will occur if this register is written while actual physical layer errors are being detected by the port. Also, there could be latency between asserting an interrupt from Output-Degraded Encountered or Output-Failed Encountered to loading this register, such that the interrupt is asserted a few cycles before the error is captured into this register.
84 of 172
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet* Name:
Bit 0
Notes
P0_ATTR_CAP_CSR
Field Name CAP_VALID_INFO
Address:
Reset Value 1b0
0x000648
Comment
Capture Valid Info: This bit is set by hardware to indicate that the Packet/control symbol capture registers contain valid information. For control symbols, only capture register 0 will contain meaningful information. Reserved. Extended Capture Information[0:15]: ECI contains the control/data character signal corresponding to each byte of captured data. ECI[0] = bit associated with P0PSC0CSR[0:7] ECI[1] = bit associated with P0PSC0CSR[8:15] ECI[2] = bit associated with P0PSC0CSR[16:23] ECI[3] = bit associated with P0PSC0CSR[24:31] ECI[4] = bit associated with P0PSC1CSR[0:7] ECI[5] = bit associated with P0PSC1CSR[8:15] ... ECI[14] = bit associated with P0PSC3CSR[16:23] ECI[15] = bit associated with P0PSC3CSR[24:31]
7:1 23:8
EXT_CAPT_INFO
0 0x0000
28:24
ERR_TYPE
0x0
Error Type: The encoded value of the bit in the Port 0 Error Detect CSR that describes the error captured in the Port 0 Error Capture CSRs. Reserved. Info Type, type of information logged: 2b00 - packet 2b01 - control symbol (only error capture register 0 is valid) 2b10 - implementation specific 2b11 - undefined.
29 31:30
INFO_TYPE
0 2b00
Table 44 Port 0 Attribute Capture CSR
Note: 1. The above register is described in the RIO Specification Part 8, sec. 2.3.2.12
Port 0 Packet/Control Symbol Capture 0 CSR
This register contains the first 4 bytes of captured packet symbol information or a control character and control symbol. Undefined results will occur if this register is written while actual physical layer errors are being detected by the port. Also, there could be latency between asserting an interrupt from Output-Degraded Encountered or Output-Failed Encountered to loading this register, such that the interrupt is asserted a few cycles before the error is captured into this register.
Name:
Bit 31:0
P0_PKT_CAP_0_CSR
Field Name CAPT_0
Address:
Reset Value All 0s
0x00064C
Comment
Capture 0: Control character and control symbol or Bytes 0 to 3 of Packet Header.
Table 45 Port 0 Packet/Control Symbol Capture 0 CSR
Note: 1. The above register is described in the RIO Specification Part 8, sec. 2.3.2.13
85 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet* Port 0 Packet Capture 1 CSR
Notes
Error capture register 1 contains bytes 4 through 7 of the packet header. Undefined results will occur if this register is written while actual physical layer errors are being detected by the port. Also, there could be latency between asserting an interrupt from Output-Degraded Encountered or Output-Failed Encountered to loading this register, such that the interrupt is asserted a few cycles before the error is captured into this register.
Name:
Bit 31:0
P0_PKT_CAP_1_CSR
Field Name CAPT_1
Address:
Reset Value All 0s
0x000650
Comment
Capture 1: Control character and control symbol or Bytes 4 to 7 of Packet Header.
Table 46 Port 0 Packet/Control Symbol Capture 1 CSR
Note: 1. The above register is described in the RIO Specification Part 8, sec. 2.3.2.14
Port 0 Packet Capture 2 CSR
Error capture register 2 contains bytes 8 through 11 of the packet header. Undefined results will occur if this register is written while actual physical layer errors are being detected by the port. Also, there could be latency between asserting an interrupt from Output-Degraded Encountered or Output-Failed Encountered to loading this register, such that the interrupt is asserted a few cycles before the error is captured into this register
Name:
Bit 31:0
P0_PKT_CAP_2_CSR
Field Name CAPT_2
Address:
Reset Value All 0s
0x000654
Comment
Capture 2: Control character and control symbol or Bytes 8 to 11 of Packet Header.
Table 47 Port 0 Packet/Control Symbol Capture 2 CSR
Note: 1. The above register is described in the RIO Specification Part 8, sec. 2.3.2.15
Port 0 Packet Capture 3 CSR
Error capture register 3 contains bytes 12 through 15 of the packet header. Undefined results will occur if this register is written while actual physical layer errors are being detected by the port. Also, there could be latency between asserting an interrupt from Output- Degraded Encountered or Output-Failed Encountered to loading this register, such that the interrupt is asserted a few cycles before the error is captured into this register.
Name:
Bit 31:0
P0_PKT_CAP_3_CSR
Field Name CAPT_3
Address:
Reset Value All 0s
0x000658
Comment
Capture 3: Control character and control symbol or Bytes 12 to 15 of Packet Header.
Table 48 Port 0 Packet/Control Symbol Capture 3 CSR
Note: 1. The above register is described in the RIO Specification Part 8, sec. 2.3.2.16
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet* Port 0 Error Rate CSR
Notes
The Port 0 Error Rate register is a 32-bit register used with the Port 0 Error Rate Threshold register to monitor and control the reporting of transmission errors.
Name:
Bit 7:0
P0_ERR_RATE_CSR
Field Name ERR_RATE_CNTR
Address:
Reset Value 0x00
0x000668
Comment
Error Rate Counter: These bits maintain a count of the number of transmission errors that have been detected by the port, decremented by the Error Rate Bias mechanism, to create an indication of the link error rate. Software should not attempt to write this field to a value higher than failed threshold trigger plus the number of errors specified in the ERR field (the maximum ERC value).
15:8 17:16
PEAK_ERR_RATE ERR_RATE_REC
0x00 2b00
Peak Error Rate: This field contains the peak value attained by the error rate counter. Error Rate Recovery: These bits limit the incrementing of the error rate counter above the failed threshold trigger: 2b00 - only count 2 errors above 2b01 - only count 4 errors above 2b10 - only count 16 errors above 2b11 - do not limit incrementing the error rate count Note that the Error Rate Counter will never increment above 0cFF, even if the combination of the settings of ERR and the failed threshold trigger might imply that it would.
23:18 31:24
ERR_RATE_BIAS
0 0x80
Reserved. Error Rate Bias: These bits provide the error rate bias value: 0x00 - do not decrement the error rate counter 0x01 - decrement every 1ms (+/-34%) 0x02 - decrement every 10ms (+/-34%) 0x04 - decrement every 100ms (+/-34%) 0x08 - decrement every 1s (+/-34%) 0x10 - decrement every 10s (+/-34%) 0x20 - decrement every 100s (+/-34%) 0x40 - decrement every 1000s (+/-34%) 0x80 - decrement every 10000s (+/-34%) Other values are reserved and will cause undefined operation.
Table 49 Port 0 Error Rate CSR
Note: 1. The above register is described in the RIO Specification Part 8, sec. 2.3.2.17
Port 0 Error Rate Threshold CSR
The Port 0 Error Rate Threshold register is a 32-bit register used to control the reporting of the link status to the system host.
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IDT 80KSBR200
Advanced Datasheet* Name:
Bit 15:0 23:16 ERR_DEG_TRIG
Notes
P0_ERR_RATE_CSR
Field Name 0 0xFF
Address:
Reset Value
0x00066C
Comment
Reserved. Error Rate Degraded Threshold Trigger: These bits provide the threshold value for reporting an error condition due to a degrading link. 0x00 - Disable the Error Rate Degraded Threshold Trigger 0x01 - Set the error reporting threshold to 1 0x02 - Set the error reporting threshold to 2 ... 0xFF - Set the error reporting threshold to 255.
31:24
ERR_FAIL_TRIG
0xFF
Error Rate Failed Threshold Trigger: These bits provide the threshold value for reporting an error condition due to a possibly broken link: 0x00 - Disable the Error Rate Failed Threshold Trigger 0x01 - Set the error reporting threshold to 1 0x02 - Set the error reporting threshold to 2 ... 0xFF - Set the error reporting threshold to 255.
Table 50 Port 0 Error Rate Threshold CSR
Note: 1. The above register is described in the RIO Specification Part 8, sec. 2.3.2.18
8.2 Configuration Registers
The configuration registers are grouped into functions with a maximum of 32 bits per register. Every configuration register is assigned a reference number for ease of location. The reference number may be used as a pointer to the address of the register whenever the configuration address is being loaded or read. The registers are read or programmed as described in the programming section 6 of this datasheet. The registers are shown with bit 0 assigned as the LSB of the register and bit 31 assigned as the MSB. Flag registers are 64 bits long with bit 63 assigned as the MSB. Within the configuration registers there are five types of bits. The bit type is shown in the column labeled "type". The five types are: HW Hard wired bits that are set by the hard wired configuration of the device. These cannot be changed by any programming method and are not affected by any of the resets. These bits may be read by any of the designated methods for reading configuration registers. These primarily deal with port structure and electrical connections. The shadow is the external pin. Bits that will enter a default mode based upon the hard-wired configuration during Master Reset. Subsequently these bits may be changed by any of the designated programming methods, and then performing a "load configuration" reset. These primarily deal with internal device structure. These registers must have a shadow register. Whenever a register containing RST bits are read by any of the designated reading methods, the actual content of the register is returned and not the content of the shadow register. Bits that may be changed at any time without a Load Configuration reset. In the event JTAG or I2C is used to alter the content, a Load Configuration Reset must be performed. These primarily deal with data routing and flagging. These registers have no shadow, except for the JTAG and I2C registers. These bits may be read by any of the designated methods. Read Only. Upon a master reset or load configuration, these will go to a known state, but once initialized they are under control of the SerB internally. sRIO Transaction IDs are an example of a register that the
RST
RW
RO
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IDT 80KSBR200
Advanced Datasheet*
Notes
RC
interface must increment with each transaction, the user may read the register, but the user cannot change the transaction IDs without causing a sequence error. Read to Clear. These bits are associated with MBIST. Contained within the MBIST register is a bit to indicate BIST is done. These bits will clear on read, only if MBIST is complete.
In addition, the configuration registers have a default mode. The defaults are shown in the column labeled "reset value". The reset values have the following form: HW 0 1 X The bit is set by the hard-wired pin configuration during reset. Whether the user can subsequently change or not depends upon the type. Protocols, port usage, etc. may affect the status of this bit. Bit defaults to zero Bit defaults to one Bit must be programmed before use. The initial state is not a concern.
8.2.1 Reset and Command Register This register may be written in order to perform a reset and other functions. The bits automatically clear after performing the function, allowing the user to write again to perform an additional reset without having to clear the bits. The use of any of these bits will clear the memory and reset all state machines. The bits are listed in priority, with Master Reset overriding Partial Reset and Partial Reset overriding Load Configuration.
Name:
Bits 0
RST_CMD_REG
Field Name MR_RST
Address:
Type RW Reset Value 1b0
0x18004
Comment Master reset: Hard Reset. The device will default to the hard wired configuration Partial Reset: Loads the shadow into the configuration registers and resets PLLs Load Configuration: Loads the shadow into the configuration registers Reserved
1
PR_RST
RW
1b0
2 31:3
LD_CFG -
RW
1b0 0
Table 51 Reset and Command Register
Note: 1. 2. 3. 4. See Section 6.3 for a complete description and functionality of these resets. Partial reset must be used if the port configuration is changed. Does not reset PLLs and cannot be used if the port configuration was changed. There is a master reset used by sRIO described in the RapidIO Part 4: Physical Layer 8/16 LP VLDS Specification.
8.2.2 Serial Port Configuration Register The Serial Port Configuration Register sets the speed of S-Port. The serial port configuration register will default to the configuration designated on the hard-wired inputs upon Master Reset. Once set, the register may be reconfigured as described. At any time, full read access is available from all indicated ports.
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IDT 80KSBR200
Advanced Datasheet* Name:
Bits 1:0 11:2 12 31:13
Notes
SPORT_CFG_REG
Field Name SP_SPEED 816_RIO_DESTID RST Type RST
Address:
Reset Value HW 0 HW 0
0x18008
Comment S-Port Speed Select: 00 = 1.25G, 01 = 2.5G, 10 = 3.125G, 11 = reserved Reserved 8 or 16 bit sRIO Destination ID: 0 = 8-bit destination ID, 1 = 16-bit destination ID Reserved
Table 52 Serial Port Configuration Register
8.2.3 Parallel Port Configuration Register The Parallel Port Configuration Register is used to set up the external QDRII SRAM memory. The default configuration is dependent upon the hard-wired inputs. A change to the contents of this register will also clear all memory contents in the queue. The registers may be read at any time, without upsetting the content.
Name:
Bit 0 1 3:2 31:4
PPORT_CFG_REG
Field Name PPORT_ON EXT_MEM_SZ HW Type RST
Address:
Reset Value HW 0 HW 0
0x18010
Comment Parallel Port On/Off: 0 = On, 1 = Off Reserved for future use External Memory Size: 00 = 36M, 01 = 72M, 1X = reserved Reserved
Table 53 P-Port Configuration Register
Note: 8.2.4 Memory Allocation Register The Memory Allocation Register is used to allocate both the internal and external memory to queue 0. Internal memory is available for allocation in block size that are 1/8th of the total SRAM capacity, hence 8 register bits[15:8]. The external memory allocation is dependent upon the size of the external memory attached, but is available in block sizes that are 1/4th of the total external memory capacity and hence 4 register bits[7:4].
Name:
Bit 3:0 7:4 15:8 31:16
MEM_ALLOC_REG
Field Name EXT_MEM_BLK INT_MEM_BLK RW RW Type
Address:
Reset Value 4h0 4h0 8hFF 0
0x18014
Comment Reserved External Memory Block Allocation Internal Memory Block Allocation Reserved
Table 54 Memory Allocation Register
Note:
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IDT 80KSBR200
Advanced Datasheet*
Notes
8.2.5 Lost Packet Replacement Register
Name:
Bit 0 31:1
LOST_PKT_REP_REG
Field Name REP_LOST_PKT Type RW
Address:
Reset Value 1b0 0
0x18030
Comment Queue 0 Replace Lost Packets: 0 = No, 1 = Yes Reserved
Table 55 Lost Packet Replacement Register
Note: 0) If a single packet is lost, it will be replaced by a dummy packet to avoid breaking the memory addresses. If more than one packet is lost, an error will be generated instead of replacing. If this bit is set to 0, the lost packet is ignored.
8.2.6 Source and Destination IDs The sRIO source and destination IDs must be programmed to access the queue. These registers are read/write from any of the access ports. sRIO may program these registers using the overall device destination ID, since direct sRIO access to the queue may otherwise not be available. In addition, a queue input or output may be programmed with either an 8 or 16 bit destination ID.
Name:
Bit 7:0 15:8 23:16 31:24
SRC_DEST_ID_REG
Field Name SRC_ID_8 SRC_ID_16 DEST_ID_8 DEST_ID_16 Type RW RW RW RW
Address:
Reset Value 8h0 8h0 8h0 8h0
0x18034
Comment Source ID is 8 bits: Defaults to base queue number Source ID is 16 bits: Defaults to zero Destination ID is 8 bits: Defaults to base queue number Destination ID is 16 bits: Defaults to zero
Table 56 Source and Destination ID Register
Note: 7:0) 15:8) 23:16) 31:24) This is the queue source ID for sRIO protocol. This is the 16 bit extension for sRIO. These bits will be compared if the queue input is enabled for 16 bits. This is the queue destination ID for sRIO. This is the 16 bit extension for sRIO on the destination ID. These bits will be appended to the sRIO header if the queue output is enabled for 16 bits.
8.2.7 Program Almost Empty / Almost Full Register The PAE and PAF flags are each eight bits long for each of the queues. The eight bits allow the flags to be placed anywhere with an accuracy of 1/256th of the total queue size. Since the queue size is programmable, PAF and PAE are proportional indications and not accurate size counts. The PAE flag is the distance from empty and the PAF flag is the distance from Full. Both may be placed anywhere in the memory, but cannot overlap to where PAF + PAE > 0FFh. These registers may be read or written from any of the sources.
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IDT 80KSBR200
Advanced Datasheet* Name:
Bit 7:0 15:8 31:16
Notes
PAE_PAF_REG
Field Name PAE_Q0 PAF_Q0 Type RW RW
Address:
Reset Value 8h0F 8h0F 16h0F0F
0x18058
Comment Program Almost Empty Program Almost Full Reserved
Table 57 PAE / PAF Register
8.2.8 Waterlevel Control Registers There is a waterlevel associated with each queue. If the waterlevel is used, the watermark should be set to zero. If the queue is a doorbell master, the watermark should be set at maximum.
Watermark Register Name:
Bit 22:0 23 31:24
WATER_MARK_ REG
Field Name WATER_MARK DW_PKT_CNT Type RW RW
Address:
Reset Value 23h0 1b0 0
0x18068
Comment Watermark: Waterlevel trigger point D-Word or Packet Count: 0 = Count Packets, 1 = Count D-Words Reserved
Table 58 Watermark Register Waterlevel Register Name:
Bit 22:0 31:23
WATER_LEVEL_ REG
Field Name WATER_LEVEL Type RO
Address:
Reset Value 23h0 0
0x1806C
Comment Waterlevel: Quantity in queue, in D-Words or packets Reserved
Table 59 Waterlevel Register Space Available Register Name:
Bit 22:0
SPACE_ AVAIL_REG
Field Name SPC_AVAIL Type RO
Address:
Reset Value 23h0
0x18070
Comment Space Available: Remaining space in D-Words, will update to available space on next few clock cycles Reserved
31:23
-
0
Table 60 Space Available Register 92 of 172 March 19, 2007
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IDT 80KSBR200
Advanced Datasheet*
Notes
Note: 1. 2. 3. The watermark is the trigger point at which the flag will be set. As a master that will always transmit new data as soon as it has arrived and been accepted, the watermark should be set to zero. D-Word or Packet count indicates whether the watermark and waterlevel are in terms of packet count or in DWord count. Flush or Single Packet determines what happens when data is sent out of the queue. a. On flush, all data in the queue is transmitted, except for new data that arrives during the flush. b. c. On Single Packet, only enough data is sent to lower the waterlevel below the watermark. Presumably, in most situations, this will be a single packet or D-Word. It should be noted that the Flush or Single Packet works with the Master/Slave selection in the Serial Port Configuration Register. If the queue is a master, the waterlevel triggers the data transmission. If a slave, the waterlevel triggers a flag only and the queue may then be read.
8.2.9 MBIST Control Register The MBIST is the primary method for memory testing. The MBIST register is one of the few configuration registers with clear on read on most bits. It is expected that all BIST will be controlled by one location/Port, preventing conflicts that may develop from interacting ports, making the clear on read a valid operational mode.
Name:
Bit 0 1 2 7:3 15:8 20:16 21 22 23 24 25 31:26
CONFIG_REG_MBIST
Field Name MBIST_START MBIST_EN I2C_MEM_EN MBIST_MEM_ERR MB_P1_SR_ME MB_P2_PP_ME MB_DONE MB_PASS RT RT RT RT RT Type RW RW RW
Address:
Reset Value 1b0 1b0 1b0 0 8h0 0 1b0 1b0 0 1b0 1b1 0
0x180C8
Comment Memory BIST Start: This bit self clears after MBIST is complete Memory BIST Enable: This bit is read/write, must stay high during MBIST I2C Memory Access Enable: Bits 1 and 2 are XOR Reserved Memory BIST Main Memory Block Error: Block 7 - 0 Reserved Memory BIST Port 1 / sRIO Memory Error Memory BIST Port 2 / Parallel Port Memory Error Reserved Memory BIST Done: If this bit is not "1", the flags from 8 -25 will not clear on read Memory BIST Pass This bit is meaningful only when bit 24 = 1 Reserved
Table 61 MBIST Control Register
Note: 1. MBIST will start when bit 1 is 1, and bit 0 changes from 0 to 1. Bit 1 will stay at "1" till MBIST is done (bit 24 becomes 1), after that, bit 1 will be self cleared to 0.
8.2.10 QBIST Control Register The QBIST accompanies the MBIST register. Most bits are clear on read.
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IDT 80KSBR200
Advanced Datasheet* Name:
Bit 0 1
Notes
CONFIG_REG_QBIST
Field Name QBIST_EN RW Type
Address:
Reset Value 0 1b0
0x180CC
Comment Reserved QBIST Enable; This bit is R/W and must stay high during QBIST. Changing from 0 to 1 will reset bits 23:8 and 25. I2C Memory Access Enable; Bits 1 and 2 are XOR Reserved QBIST Error Counter Block 7 - 0 Reserved QDR Memory BIST Pass Reserved
2 7:3 23:8 24 25 31:26
I2C_MEM_EN QBIST_ERR_CNT QBIST_PASS -
RW
1b0 0
RC
16h0 0
RC
1b1 0
Table 62 QBIST Control Register
Note: QBIST will start once QBIST enable changes from 0 to 1 and stop when QBIST enable changes from1 to 0. 2:1) Bits 1 and 2 are exclusive of each other. 23:8) The error counter will wrap around once saturated. The user may check this counter against a timer to determine the bit error rate. 8.2.11 JTAG Device ID Register JTAG Device Identification register is provided for use with identifying the device. The content is duplicated here to allow access from all available access ports.
Name:
Bit 0 11:1 27:12
JTAG_DEVICE_ID
Field Name STDRD_BIT IDT_JTAG_ID IDT_PART_NUM Type HW HW HW
Address:
Reset Value 0b1 0x033 0x04F0
0x180D0
Comment Standard Bit: Standard bit[0] = 1 per IEEE-2001. IDT JTAG Identification: JTAG Vendor ID for IDT. IDT JTAG Part Number: JTAG Device ID for SerB. 0x4F0 - sRIO / 18Meg 0x4F1 - sRIO / 9Meg IDT Version Number: Version number of SerB = 0.
31:28
IDT_VER_NUM
HW
0x0
Table 63 JTAG Device ID Register
8.2.12 Case Scenario Configuration Registers Case scenarios are used to generate sRIO outgoing packet headers when the SerB initiates a packet. In the case of response packets, the incoming packet is used instead. A complete description is provided in the Case Scenario section. These registers are read/write from any of the access ports. The default values are functionally don't care, since they cannot be used until programmed.
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IDT 80KSBR200
Advanced Datasheet* Case Scenario Packet Header Register Name:
Bit 1:0 3:2 7:4 15:8 23:16 27:24 31:28
Notes
CS0_PKT_HEADER
Field Name PRIORITY TT FTYPE TARGETADDR TARGETADDR16 TTYPE Type RW RW RW RW RW RW
Address:
Reset Value 2b0 2b0 4h0 4h0 8h0 4h0 0
0x18400
Comment sRIO Priority Packet Transaction Type, 00 = 8 bit, 01 = 16 bit sRIO Transaction Format Type Destination ID for the transmission Extension for 16 bit if TT = 01; see note 1 Transaction Type (sub group of FTYPE) Reserved
Table 64 Case Scenario Packet Header Register
Note: 1:0) 3:2) 7:4) 15:8) 23:16) 27:24) SIZE: PRIORITY - The priority for the sRIO packet header. CR is set to zero and ignored as part of the priority. Default priority should be 00h, low priority. TT - The sRIO transaction type. If set to 00h, the transaction is 8 bits, if set to 01h, the transaction is 16 bits. Other TT values are invalid. FTYPE - Defined in the sRIO specification, part 1, section 4.1. The only FTYPEs supported are types 5 (WRITE) and 6 (SWRITE). TARGET ADDRESS - The destination ID for the packet to be sent. This byte will be included in all packets using this case scenario. TARGET ADDRESS, x16 - The MSB of the address if the sRIO transaction is 16 bits. If TT = 00, the target address MSBs are used. TTYPE - The sub transaction to the FTYPE defined in the same location as FTYPE. If FTYPE is 5 the only TTYPEs supported are NWRITE and NWRITE_R. The size is set by the hardware and should not be part of the case scenario. See sRIO spec., section 4.1.2.
Case Scenario Start Address Register
The starting address for memory writes when performing SWRITE and NWRITE operations with this case scenario. The address contained in the packet will increment appropriately starting from this location. Upon a wrap or reset, the address will return to this value.
Name:
Bit 30:0 31
CS0_STRT_ADDR
Field Name STRT_ADDR Type RW
Address:
Reset Value 31h0 0
0x18404
Comment Start Address: Starting memory address for sRIO Reserved
Table 65 Case Scenario Start Address Register Case Scenario Next Address Register
95 of 172
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IDT 80KSBR200
Advanced Datasheet*
Notes
The current value for the ADDRESS. Whenever a new case scenario is programmed, this value will be set to be identical to the START ADDRESS. The address will increment by the quantity of data transmitted with every packet. The NEXT ADDRESS will not rise beyond the STOP ADDRESS. If the Wrap or Stop bit in the following register is set to WRAP, the NEXT address will reset to the START ADDRESS whenever STOP ADDRESS has been hit. If the wrap occurs in the middle of the packet, the NEXT ADDRESS will increment after the reset to indicate how much of the tail of the packet was written after the wrap.
Name:
Bit 30:0 31
CS0_NEXT_ADDR
Field Name NEXT_ADDR Type RW
Address:
Reset Value 31h0 0
0x18408
Comment Next Address: Current memory address for sRIO Reserved
Table 66 Case Scenario Next Address Register Case Scenario Stop Address Register
The final incremental address for writing. The higher address may be included in the sRIO packet header, but in some cases the packet length may cause a write to an address higher than this value, in case of an overflow. The START ADDRESS and STOP ADDRESS should be identical if the user does not want the address issued in the packet header to increment.
Name:
Bit 30:0 31
CS0_STOP_ADDR
Field Name STOP_ADDR Type RW
Address:
Reset Value 31h0 0
0x1840C
Comment Stop Address: Maximum memory address for sRIO Reserved
Table 67 Case Scenario Stop Address Register Case Scenario Frame Register Name:
Bit 9:0 14:10 15 23:16 27:24 28
CS0_FRAME_REG
Field Name FRAME_SIZE FRAME_OFFSET TALLY_FLAG FRAME_COUNT MEM_WRAP_STP RW Type RW RW RW RW
Address:
Reset Value 10h0 5h0 1b0 8h0 0 1b0
0x18410
Comment Frame size Frame Offset: Offset on first count Set Tally Flag: 1 = Send doorbell to Dest ID on count = size Frame Count: Counts frame, reset on doorbell Reserved Memory Wrap or Stop: Stop or Wrap on STOP Address
Table 68 Case Scenario Frame Register
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IDT 80KSBR200
Advanced Datasheet*
Bit 29 31:30 Field Name FLAG_WRAP_STP FRAME_CNT Type RW RO Reset Value 1b0 2b0 Comment Set Flag on Wrap or Stop: Used with either stop or wrap The highest two bits of the frame count
Notes
Table 68 Case Scenario Frame Register
Note: 9:0) 14:10) 15) 23:16) FRAME SIZE - The maximum frame size of the data for the TI application. Whenever the FRAME SIZE has been hit, a doorbell will be issued to wake up the DSP (if doorbell is enabled). FRAME OFFSET - TI requested that we have an offset to the first FRAME SIZE to allow them to compensate for delays through the system. DOORBELL - This bit indicates that the FRAME SIZE is active and the doorbell should be sent when FRAME SIZE is hit. FRAME COUNT - The location for the current value of the counter for FRAME SIZE. When the count reaches FRAME SIZE and the doorbell is active, the doorbell will be sent and FRAME COUNT will reset to zero. Lite Dest ID - Lite protocols have only four bits to select either a destination ID or Case Scenario. To solve the problem of what happens when a Lite protocol selects a case scenario and then the packet needs to be loaded into a queue, the Lite Dest ID is placed in the case scenario. The queue inputs may be programmed to allow selection of multiple queues with the same destination ID. Memory Wrap or Stop - Defines whether the NEXT ADDRESS will wrap or stop when it hits STOP ADDRESS. 0 = WRAP, 1 = STOP. Memory Doorbell - Indicates whether a doorbell should be sent when the NEXT ADDRESS hits the STOP ADDRESS. Frame size plus offset should not exceed ten bits.
27:24)
28) 29) 31:30)
8.2.13 Missing Packet Detection Registers Missing Packet Detection mechanism consists of Memory Start Address, Current Memory Address, Memory Address Increment and Memory Stop Address registers and are fully described in the section on Missing Packet Detection and Replacement.
Memory Start Address Register Name:
Bit 30:0 31
MEM_STRT_ADDR
Field Name MEM_STRT_ADDR Type RW
Address:
Reset Value 31h0 0
0x18580
Comment Memory Start Address: Start address for missing packet detection Reserved
Table 69 Missing Packet Start Address Register Current Memory Address Register
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet* Name:
Bit 30:0 31
Notes
CNT_MEM_ADDR
Field Name CNT_MEM_ADDR Type RW
Address:
Reset Value 31h0 0
0x18584
Comment Current Memory Address: Used to hold the current memory address Reserved
Table 70 Missing Packet Current Address Register Memory Address Increment Register Name:
Bit 5:0 31:6
MEM_ADDR_MEM
Field Name MEM_ADDR_INC Type RW
Address:
Reset Value 6h0 0
0x18588
Comment Memory Address Increment: Used to predict next current memory address Reserved
Table 71 Missing Packet Address Increment Register Memory Stop Address Register Name: MEM_STOP_ADDR
Field Name MEM_STOP_ADDR Type RW
Address:
Reset Value 31h0 0
0x1858C
Comment Memory Stop Address: The last allowed memory address Reserved
Bit 30:0 31
Table 72 Missing Packet Stop Address Register
Note: 1. The stop address must align with the start address and the address increment. A misalignment may cause the stop address to be missed.
8.2.14 Packet Interval Timer Register The PPS has no storage capability and cannot accept packets faster that its processing capability. To solve this problem, both the data packets and the doorbells exiting S-Port 1 may be timed with a programmable interval timer. The interval timer uses the PHY clock 156.25MHz as the tick. A set interval is programmed into the PPS Packet Interval Timer Register. When a packet is sent using sRIO out S-Port 1, the interval timer will begin counting down, starting when the packet has completed. When the counter reaches zero, a following packet may be sent. The PPS acceptance of doorbells is much faster than data packets: therefore, they will be accomplished by a second counter with the countdown initiated when the doorbell starts.
Data Packet Interval Timer Register
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IDT 80KSBR200
Advanced Datasheet* Name:
Bit 15:0 31:16
Notes
DATA_ ITV_TIME
Field Name DATA_PKT_TIME Type RW
Address:
Reset Value 16h0 0
0x185C0
Comment Data Packet Timer: Counts down, holds at 00h Reserved
Table 73 Data Packet Interval Timer Register Doorbell Packet Interval Timer Register Name:
Bit 15:0 31:16
DB_ITV_ TIME
Field Name DBELL_PKT_TIME Type RW
Address:
Reset Value 16h0 0
0x185C4
Comment Doorbell Packet Timer: Counts down, holds at 00h Reserved
Table 74 Doorbell Packet Interval Timer Register
8.2.15 Missing Packet Size Register This register is used to set the size of missing/replacement packet payload.
Name:
Bit 5:0 31:6
MISS_PKT_SZ
Field Name MISS_PKT_SZ Type RW
Address:
Reset Value 6h0 0
0x185CC
Comment Missing Packet Size: Size for inserted packet payload Reserved
Table 75 Missing Packet Size Registers
8.2.16 Missing Packet Address Logging Register 1 Upon the detection of a missing packet, the address of the next valid packet will be loaded into this register. The user may then poll this register to identify the address.
Name:
Bit 30:0 31
MISS_PKT_LOG_1
Field Name MIS_PKT_LOG_1 Type Note
Address:
Reset Value 31h0 0
0x19D60
Comment Missing Packet Address Log: The address of the first valid packet following a missing packet Reserved
Table 76 Missing Packet Address Logging Register
Note: 30:0) The address of the next valid packet following a missing packet is loaded into this register whenever the missing packet flag is toggled. When either the Missing Packet Flag register is read and cleared, this register will also clear.
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IDT 80KSBR200
Advanced Datasheet*
Notes
8.2.17 Missing Packet Address Logging Register 2 This register is identical to the Missing Packet Address Logging Register, except it is associated with the "Missing
Packet Programmable Flag Register" instead of the "Missing Packet Flag Register".
Name:
Bit 30:0 31
MISS_PKT_LOG_2
Field Name MIS_PKT_LOG_2 Type Note
Address:
Reset Value 31h0 0
0x19F20
Comment Missing Packet Address Log for TI DSP: The address of the first valid packet following a missing packet Reserved
Table 77 Missing Packet Address Logging Register for TI DSP
Note: 30:0) The address of the next valid packet following a missing packet is loaded into this register whenever the missing packet flag is toggled. When either the Missing Packet Flag register is read and cleared, this register will also clear.
8.3 SerB Error Counter Registers
8.3.1 S-Port Data Packet Received Counter As part of the device error management, there is a data packet received counter associated with S-Port. This counter is reset by reading. The counter will count every data packet entering the port. Upon reaching full count, the packets will remain at full count and will not wrap.
Name:
Bit 31:0
DATA_PKT_RCV_CNT
Field Name SDP_RX_CNT Type RW
Address:
Reset Value 32h0
0x185DC
Comment S-Port Data Packet Received Counter: Reset 0 by reading
Table 78 S-Port Data Packet Received Counter
8.3.2 S-Port Data Packet Transmitted Counter As part of the device error management, there is a data packet transmitted counter associated with S-Port. This counter is reset by reading. The counter will count every data packet leaving the port. Upon reaching full count, the packets will remain at full count and will not wrap.
Name:
Bit 31:0
DATA_PKT_XMT_CNT
Field Name SDP_TX_CNT Type RW
Address:
Reset Value 32h0
0x185E0
Comment S-Port Data Packet Transmitted Counter: Reset 0 by reading
Table 79 S-Port Data Packet Transmitted Counter
8.3.3 S-Port Priority Packet Received Counter As part of the device error management, there is a priority packet received counter associated with S-Port. This counter is reset by reading. The counter will count every priority packet entering the port. Upon reaching full count, the packets will remain at full count and will not wrap.
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IDT 80KSBR200
Advanced Datasheet* Name:
Bit 31:0
Notes
PRIO_PKT_RCV_CNT
Field Name SPP_RX_CNT Type RW
Address:
Reset Value 32h0
0x185E4
Comment S-Port Priority Packet Received Counter: Reset 0 by reading
Table 80 S-Port Priority Packet Received Counter
Note: 1. Single 32-bit aggregate counter to count all the non-blocking (Config Write Request and Config Read Request) and blocking (sRIO NREAD and Doorbell Request Frame and Lite Read) priority packets being received on Port 1 Interface.
8.3.4 S-Port Priority Packet Transmitted Counter As part of the device error management, there is a priority packet transmitted counter associated with S-Port. This counter is reset by reading. The counter will count every priority packet leaving the port. Upon reaching full count, the packets will remain at full count and will not wrap.
Name:
Bit 31:0
PRIO_PKT_XMT_CNT
Field Name SPP_TX_CNT Type RW
Address:
Reset Value 32h0
0x185E8
Comment S-Port Priority Packet Transmitted Counter: Reset 0 by reading
Table 81 S-Port Priority Packet Transmitted Counter
Note: 1. Single 32-bit aggregate counter to count all the priority packets (Doorbell Request, NWRITE Response, Config Read Response, Config Write Response and Doorbell Response) being transmitted on Port 1 Interface.
8.3.5 S-Port Packet Received Counters As part of the device error management, there is a packet received counter associated with the queue. These counters are reset by reading. Each counter will count every packet entering the queue. Upon reaching full count, the packets will remain at full count and will not wrap.
Name:
Bit 31:0
SP_PKT_RCV_CNT
Field Name SPKT_RCV_CNT Type RW
Address:
Reset Value 32h0
0x185EC
Comment S-Port Packet Received Counter: Reset 0 by reading
Table 82 S-Port Packet Received Counter
8.3.6 S-Port Packet Transmitted Counters As part of the device error management, there is a packet transmitted counter associated with the queue. These counters are reset by reading. Each counter will count every packet sent from the queue. Upon reaching full count, the packets will remain at full count and will not wrap.
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IDT 80KSBR200
Advanced Datasheet* Name:
Bit 31:0
Notes
SP_PKT_XMT_CNT
Field Name SPKT_XMT_CNT
Address:
Type RW Reset Value 32h0
0x1860C
Comment S-Port Packet Transmitted Counter: Reset 0 by reading
Table 83 S-Port Packet Transmitted Counter
8.4 SERDES Quad Control Register
The sRIO specification has defined registers for use in configuring and controlling the 1x/4x Quad Serdes sRIO port (SPort 1 on the SerB). The SerB shall utilize the standard register and observe standard 1x/4x configuration protocols. For the rest of the serial ports definition, refer to "RapidIO Interconnect Specification Part VI: Physical Layer 1x/4x LPSerial Specification.
Name:
Bit 1:0 4:2
SERDES_QUAD_CTRL
Field Name TCOEFF[2:0] RW Type
Address:
Reset Value 0 3b0
0x18C30
Comment Reserved Transmit pre-emphasis control: 000 = 0% emphasis 001 = 6.5% emphasis 010 = 13% emphasis 011 = 19.5% emphasis 100 = 26% emphasis 101 = 32.5% emphasis 110 = 39% emphasis 111 = 45.5% emphasis Reserved Tx drive strength select 000 = maximum drive strength 010 = sRIO long haul 100 = sRIO short haul 111 = minimum drive strength Reserved
6:5 9:7
TXDRVSEL RW
0 3b010
31:10
-
0
Table 84 SERDES Quad Control Register
8.5 Flag and Flag Mask Registers
The flag registers are 32-bit registers and include an additional 32-bit register for the flag masks. Each register contains a maximum of 8 flags plus the masks and destination IDs associated with those flags. The typical flag register content is shown below table. The flags within a register are selected to generate same interrupt or generate doorbells destined for the same location. The interrupting flag may individually be identified by the register contents that may be read or sent with a doorbell. Contained within each flag register is a series of four mask registers for the flags. The flag mask registers are used to create doorbells and interrupts. This means there are five register locations associated with each flag. The content of each flag register is available for reading at any time by any of the following methods: sRIO commands I2C Interface JTAG
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IDT 80KSBR200
Advanced Datasheet*
Notes
# 7-0 8 9 11-10 15-12 23-16 31-24 39-32 47-40 55-48 63-56 Signal FLAGS TT WR32 PRIO RES DESTID DESTID MASK RES MASK MASK Stat X RW RW RW X RW RW RW X RW RW Description There are up to 8 flags contained in the register Defines whether the sRIO doorbell is an 8 or 16 bit destination ID 0 = Write 8 bits (clear flags only), 1 = Write 32 bits (write new dest IDs) Priority for Doorbell packet Unused bits Destination ID for sRIO Doorbell Destination ID for sRIO Doorbell, for 16 bit extension S-Port Doorbell Mask Unused bits Interrupt 0 Mask Interrupt 1 Mask
Table 85 Flag and Flag Mask Register
Note: 7:0) These 8 bits within the register are where the flags are stored. As noted below, there is a name, a status for the flag and a description of the flag shown for each flag. Some flags are updated real time, while others latch and must be cleared. Designates whether source and destination IDs of the doorbell should use 8 bits or 16 bits. The true TT is two bits, but only one bit is required to make 8/16 designation. Wr32 designates whether a write to this register is 8 bits or 32 bits. An 8 bit write would write a mask to the flag portion of the register to clear the masked flags. Within the mask, any flag that is overwritten by "1" would be cleared. Any flag overwritten with a "0" would be unaffected by the write. A 32 bit write to this register would be required to alter the destination ID and TT portions of the register. In a 32 bit write, the flags could be cleared or left unaffected, based upon the state of the 8 LSBs of the write, the same as with the 8 bit write. Note that RT flags cannot be cleared. These bits indicate the priority that should be used for any sRIO doorbell packet. Any unused bits are indicated as Reserved. This is the 8 bit destination ID for a doorbell on S-Port if the mask bits 8-15 allow a doorbell to be created. This is the 16 bit extension to the destination ID for doorbells on S-Port if using sRIO extended addresses. These are the mask bits for the flags. Any unmasked flag will cause a doorbell to be sent on S-Port. Reserved for future use. This is the mask for the Int 0 interrupt pin. This is the mask for the Int 1 interrupt pin.
8) 9)
11:10) 15:12) 23:16) 31:24) 39:32) 47:40) 55:48) 63:56)
8.5.1 Key to the Flag Registers The flag registers are listed in the order of priority for doorbells and interrupts. All masks power up and reset to fully masked and are enabled by unmasking the bits. All flag register tables are shown with the following column headings and symbols within the register: #: The bit location within the designated register Signal: An abbreviated name for the Flag Stat: Indicates whether the flag may be cleared - CL: Clearable flag. These flags will latch upon toggling and must be cleared by a write to the register - RT: Indicates the flag is a real time and always represents current conditions. Clearing a RT flag is not possible RW: Used with masks to indicate the bits are Read/Write through a configuration read/write
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IDT 80KSBR200
Advanced Datasheet*
Notes
8.5.2 sRIO Link Status The RapidIO "Error Management Extensions Specification" requires specific Configuration Status Registers at designated addresses. These CSRs are described in section 2 of the identified spec, and should be referenced for more specific information. 8.5.3 S-Port Link Status The flags of the "S-Port Link Status". This flag register is used to identify error that is not covered by the sRIO Error Management Extensions Specification.
Name: SP_LNK_STAT_FLAG SP_LNK_STAT_MASK Address: 0x19C04 0x19CC4
This register cannot generate an sRIO packet.
# 3:0 4 5 6 7 8 9 11-10 15-12 23-16 31-24 39-32 47-40 55-48 63-56 Signal RETRY JTAG EME TT WR32 PRIO DESTID DESTID MASK MASK MASK RW RW RW RW RW RW RW RW CL CL CL Stat Description Reserved sRIO Doorbell Response with RETRY received JTAG error sRIO Error Management Extension Interrupt Unused bit Defines whether the sRIO doorbell is an 8 or 16 bit destination ID 0 = Write 8 bits (clear flags only), 1 = Write 32 bits (write new dest IDs) Priority for Doorbell packet Unused bits Destination ID for sRIO Doorbell Destination ID for sRIO Doorbell, for 16 bit extension S-Port Doorbell Mask Unused bits Interrupt 0 Mask Interrupt 1 Mask
Table 86 S-Port 1 Link Status for Lite Register
Note: 4) Indicates that in response to a previously sent doorbell a "RETRY" indication was received.
8.5.4 Device Configuration Error These flags are generated whenever a configuration error occurs. When a configuration error occurs the SerB will not function, however these flags may be masked to create doorbells and interrupts on the ports designated by the masks. All of these flags are real time (RT) and cannot be cleared except by re-configuring the offending register.
Name: CONFIG_ERR_FLAG CONFIG_ERR_MASK Address: 0x19C0C 0x19CCC
If this register generates an sRIO packet, the packet will be a doorbell.
# 0 Signal ERR Stat RT Description External memory is allocated but not available
Table 87 Device Configuration Error Register 104 of 172 March 19, 2007
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IDT 80KSBR200
Advanced Datasheet*
# 7-1 8 9 11-10 15-12 23-16 31-24 39-32 47-40 55-48 63-56 Signal TT WR32 PRIO DESTID DESTID MASK MASK MASK RW RW RW RW RW RW RW RW Stat Description Reserved Defines whether the sRIO doorbell is an 8 or 16 bit destination ID 0 = Write 8 bits (clear flags only), 1 = Write 32 bits (write new dest IDs) Priority for Doorbell packet Unused bits Destination ID for sRIO Doorbell Destination ID for sRIO Doorbell, for 16 bit extension S-Port Doorbell Mask Unused bits Interrupt 0 Mask Interrupt 1 Mask
Notes
Table 87 Device Configuration Error Register
Note: 0) Error - This flag indicates that the SerB is programmed to have more memory than is actually attached to P-Port.
8.5.5 sRIO DMA Status Register These flags are generated whenever an sRIO error occurs that is not covered by one of the error flags defined in the sRIO specification. These errors are monitored by the Case Scenarios, so there is one flag register per case scenario.
Name: CS0_DMA_STAT_FLAG Address: CS0_DMA_STAT_MASK 0x19C10 0x19CD0
If this register generates an sRIO packet, the packet will be a doorbell.
# 0 1 7-2 8 9 11-10 15-12 23-16 31-24 39-32 47-40 55-48 63-56 Signal MEMSTOP TALLY1 TT WR32 PRIO DESTID DESTID MASK MASK MASK RW RW RW RW RW RW RW RW Stat RT RT Description sRIO NEXT ADDRESS has reached STOP ADDRESS The packet tally counter wrapped on S-Port Reserved Defines whether the sRIO doorbell is an 8 or 16 bit destination ID 0 = Write 8 bits (clear flags only), 1 = Write 32 bits (write new dest IDs) Priority for Doorbell packet Unused bits Destination ID for sRIO Doorbell Destination ID for sRIO Doorbell, for 16 bit extension S-Port Doorbell Mask Unused bits Interrupt 0 Mask Interrupt 1 Mask
Table 88 sRIO DMA Status Register
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IDT 80KSBR200
Advanced Datasheet*
Notes
Note: 0) Memory Stop - The sRIO memory address has incremented to or beyond the stop address. This flag may be used to send a doorbell if the address reaches the stop address (triggering the flag condition), the flag will remain active until software writes a "1" to clear the flag. Tally1 - The packet tally counter will wrap. If the user whishes to know it wrapped, the flag may be used.
1)
8.5.6 Missing 2 Packet Flag Register If missing 2 packet is turned on and two or more packets are missing, the flags of this register will be used. Note that If this register is read and cleared, the "Missing Packet Address Logging Register 1" will also be cleared.
Name: MISS2_PKT_FLAG MISS2_PKT_MASK Address: 0x19C50 0x19D10
If this register generates an sRIO packet, the packet will be a doorbell.
# 0 7-1 8 9 11-10 15-12 23-16 31-24 39-32 47-40 55-48 63-56 Signal MISSIN2 TT WR32 PRIO DESTID DESTID MASK MASK MASK RW RW RW RW RW RW RW RW Stat CL Description Two or more sRIO packets were detected as missing Reserved Defines whether the sRIO doorbell is an 8 or 16 bit destination ID 0 = Write 8 bits (clear flags only), 1 = Write 32 bits (write new dest IDs) Priority for Doorbell packet Unused bits Destination ID for sRIO Doorbell Destination ID for sRIO Doorbell, for 16 bit extension S-Port Doorbell Mask Unused bits Interrupt 0 Mask Interrupt 1 Mask
Table 89 Missing Packet Flag Register
Note: 0) Missing 2 - If two or more packets are missing, they cannot be replaced. This flag indicates that a catastrophic error has occurred in the PPS application.
8.5.7 FIFO Empty Flag Register If this register generates an sRIO packet, the packet will be a doorbell.
Name: FIFO_EMPTY_FLAG FIFO_EMPTY_MASK
Signal EF PAE PR W Stat RT RT RT RT
Address:
0x19C60 0x19D20
# 0 1 2 3 7-4
Description Queue 0, Empty Flag Queue 0, Programmable Almost Empty Queue 0, Packet Ready Queue 0, Waterlevel Exceeds Packet Count Reserved
Table 90 FIFO Queue Empty Flag Register 106 of 172 March 19, 2007
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IDT 80KSBR200
Advanced Datasheet*
# 8 9 11-10 15-12 23-16 31-24 39-32 47-40 55-48 63-56 Signal TT WR32 PRIO DESTID DESTID MASK MASK MASK RW RW RW RW RW Stat RW RW RW Description Defines whether the sRIO doorbell is an 8 or 16 bit destination ID 0 = Write 8 bits (clear flags only), 1 = Write 32 bits (write new dest IDs) Priority for Doorbell packet Unused bits Destination ID for sRIO Doorbell Destination ID for sRIO Doorbell, for 16 bit extension S-Port Doorbell Mask Unused bits Interrupt 0 Mask Interrupt 1 Mask
Notes
Table 90 FIFO Queue Empty Flag Register
Note: 0) 1) 2) 3) 7-4) EF = No data remains in queue PAE = Programmable on 1/256th portions of queue memory PR = Full packet ready for reading, reading one byte or more will kill flag W = Waterlevel is at or past the watermark (either byte or packet count) Res = Reserved bit
8.5.8 FIFO Full Flag Register If this register generates an sRIO packet, the packet will be a doorbell.
Name: FIFO_FULL_FLAG FIFO_FULL_MASK
Signal FF PAF SA TT WR32 PRIO DestID DestID MASK MASK MASK RW RW RW RW RW RW RW RW Stat RT RT RT
Address:
0x19C64 0x19D24
# 0 1 2 7-3 8 9 11-10 15-12 23-16 31-24 39-32 47-40 55-48 63-56
Description Queue 0, Full Flag, Incoming packet rejected Queue 0, Programmable Almost Full Queue 0, One or more Max Sized Packet Space Available Reserved Defines whether the sRIO doorbell is an 8 or 16 bit destination ID 0 = Write 8 bits (clear flags only), 1 = Write 32 bits (write new dest IDs) Priority for Doorbell packet Unused bits Destination ID for sRIO Doorbell Destination ID for sRIO Doorbell, for 16 bit extension S-Port 1 Doorbell Mask Unused bits Interrupt 0 Mask Interrupt 1 Mask
Table 91 FIFO Queue Full Flag Register
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Advanced Datasheet*
Notes
Note: 0) 1) 2) FF = No space remains in queue, the entire incoming packet was rejected PAF = Programmable on 1/256th portions of queue memory SA = Space available for one full sized packet. A doorbell will be sent whenever the flag changes state. Flag is inactive whenever the incoming packet may prevent an additional packet entering.
8.5.9 DSP Interrupt Flag Register In the TI application, if a doorbell is sent to the DSP, it must have a programmable content. To solve the problem, unmasked flags may send a doorbell to the DSP upon toggling. When enabled, every unmasked flag (except the packet tally flags) will send a doorbell with the programmed content to the DSP at the programmed destination ID. This register sends an sRIO doorbell on S-Port and is not capable of generating an interrupt on Int 0 or Int 1. Since it has programmable content, there is no register number associated with this register.
Name: DSP_INT_FLAG DSP_INT_MASK Address: 0x19CA0 0x19E60
If this register generates an sRIO packet, the packet will be a doorbell.
# 0 7-1 8 9 11-10 15-12 23-16 31-24 39-32 47-40 63-48 Signal FLAG TT WR32 PRIO DESTID DESTID MASK POINTER RW RW RW RW RW RW RW Stat RT Description The Aggregate of all unmasked flags Reserved Defines whether the sRIO doorbell is an 8 or 16 bit destination ID 0 = Write 8 bits (clear flags only), 1 = Write 32 bits (write new dest IDs) Priority for Doorbell packet Unused bits Destination ID for sRIO Doorbell Destination ID for sRIO Doorbell, for 16 bit extension S-Port Doorbell Mask Unused bits Programmable Doorbell Contents
Table 92 DSP Interrupt Flag Register
Note: 0) 24:16) 39:32) This flag will toggle if any other unmasked flag toggles. This flag may be cleared only by clearing the source flag. This is the destination ID for the DSP that must receive the programmed doorbell. This may be any destination. The doorbell is turned on and off by masking bit 0. This mask does not affect the source flags. The source flags each have their own flags and masks. The Int 1 mask associated with each individual flag is used to enable the flags to toggle the DSP Interrupt Flag. The tally flag should always be masked off in Int 1 masks on the individual flag registers to avoid toggling the DSP Interrupt Flag. Int 1 and the DSP mask share a mask and must toggle due to the same flags. The content of the doorbell is a 16 bit user programmable pointer.
63:48)
8.5.10 Tally Doorbell Flag Register If the "Tally 1" flag in the sRIO DMA Status Information Register toggles in the TI application, the user may wish to send a doorbell to the DSP. The content of the doorbell is user programmable, to allow the user to select an interrupt within the DSP. This doorbell does not interfere with any doorbells or interrupts generated by the sRIO DMA Status Information Register.
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IDT 80KSBR200
Advanced Datasheet*
Notes
This register sends an sRIO doorbell on S-Port and is not capable of generating an interrupt on Int 0 or Int 1, therefore there is no register number.
Name: CS0_TALY_DBEL_FLAG Address: CS0_TALY_DBEL_MASK 0x19E10 0x19ED0
If this register generates an sRIO packet, the packet will be a doorbell.
# 0 1 7-2 8 9 11-10 15-12 23-16 31-24 39-32 47-40 63-48 Signal TALLY1 TT WR32 PRIO DESTID DESTID MASK POINTER RW RW RW RW RW RW RW CL Stat Description Reserved The Packet Tally Counter Wrapped on S-Port Unused bits Defines whether the sRIO doorbell is an 8 or 16 bit destination ID 0 = Write 8 bits (clear flags only), 1 = Write 32 bits (write new dest IDs) Priority for Doorbell packet Unused bits Destination ID for sRIO Doorbell Destination ID for sRIO Doorbell, for 16 bit extension S-Port Doorbell Mask Unused bits Programmable Doorbell Contents
Table 93 Tally Doorbell Flag Register
Note: 1) 24:16) 39:32) 63:48) This flag is identical to the flag in the "sRIO DMA Status Information" register. This is the destination ID for the DSP that must receive the tally indication doorbell. It is not required that this be the same destination as in the "sRIO DMA Status Information" register. The doorbell is turned on and off by masking bit 1. The content of the doorbell is a 16 bit user programmable pointer.
8.5.11 Missing 2 Packet Programmable Flag Register If missing 2 packet is turned on and two or more packets are missing, this register will allow a programmable doorbell to be sent to a designated sRIO destination ID. Note that If this register is read and cleared, the "Missing Packet Address Logging Register 2" will also be cleared.
Name: MISS2_PGRM_FLAG MISS2_PGRM_MASK Address: 0x19E50 0x19F10
If this register generates an sRIO packet, the packet will be a doorbell.
# 0 7-1 8 9 11-10 Signal MISSIN2 TT WR32 PRIO RW RW RW Stat CL Description Two or more sRIO packets were detected as missing Reserved Defines whether the sRIO doorbell is an 8 or 16 bit destination ID 0 = Write 8 bits (clear flags only), 1 = Write 32 bits (write new dest IDs) Priority for Doorbell packet
Table 94 Missing Packet Programmable Flag Register 109 of 172 March 19, 2007
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# 15-12 23-16 31-24 39-32 47-40 63-48 Signal DESTID DESTID MASK POINTER RW RW RW RW Stat Description Unused bits Destination ID for sRIO Doorbell Destination ID for sRIO Doorbell, for 16 bit extension Programmable sRIO Doorbell Mask Unused bits Programmable Doorbell Contents
Notes
Table 94 Missing Packet Programmable Flag Register
Note: 0) Missing 2 - If two or more packets are missing, they cannot be replaced. This flag indicates that a catastrophic error has occurred in the PPS application. The programmable contents of locations 63-48 will be sent to the destination ID in locations 31-16.
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9.0 Reset and Initialization
The SerB does not require specific power sequencing between any of the core and I/O supplies.
Figure 11 Reset Timeline
To reset the device, first reset signal has to be de-asserted (Reset Low), and it is asserted after 5 REF_CLK cycles. 4096 REF_CLK cycles later, the device completes the reset process. Once completed, access to the SerB from any and all interfaces is possible and the SerB is fully functional. COntrol and data traffic will not be accepted by the SerB until this process is fully completed.
9.1 Speed Select (SPD[1:0])
There are 2 port speed select pins. These pins are used to chose the initial speed on sRIO ports. The selection table is given below:
etaR stroP
1.25Gbps 2.5Gbps 3.125Gbps Reserved Value on the Pins (SPD1 SPD0) 00 01 10 11
Table 95 Port Speed Selection Pin Values
9.2 sRIO Reset Control Symbol
The sRIO Reset Control Symbol is defined by the RIO spec to perform a master reset on the target device. It is a link level reset and must be received four times to perform the reset. Despite it being a control symbol generated at the link level, the use of the reset is generally instructed from higher-level authority than the link. The PPS has taken the control symbol and has allowed the user to program the severity of the reset either as a full master reset, or as an sRIO port reset only. The PPS also has the capability of receiving instructions from the DSP to send a control symbol on any one of its ports to reset other attached devices. The SerB will not have the capabilities of the PPS and will perform only a full Master Reset whenever the sRIO reset control symbol has been received four times. The count of four will reset whenever a packet other than an sRIO reset control symbol is successfully received. The control symbol has no capability to form anything other than a Master Reset. Any other sRIO resets must be received in the form of type 8 maintenance packets. More details on the control symbol can be found in section 3.4.5.1 of Physical Layer x1/x4 LP-Serial Specification.
9.3 JTAG Reset
At Power-Up, TRST must be asserted LOW to bring the TAP controller up in a known, reset state. Per IEEE 1149.1 specification, the user can alternatively hold TMS pin high while clocking TCK five times (minimum) to reset the controller. To deactivate JTAG, TRST should be tied low so that the TAP controller remains in a known state at all times. All of the other JTAG input pins are internally biased in such a way that by leaving them unconnected they are automatically disabled. Note that JTAG inputs are OK to float because they have leakers (as required by IEEE 1149.1 specification).
9.4 System Initialization
The SerB will automatically configure itself upon power up to the default configuration set by the hard-wired inputs. For the duration of the default configuration, the SerB will not accept packets on either serial port. Once the SerB has achieved the default configuration, the ports will become active and may accept data. If additional programming is to be completed
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after the default configuration is active, the user should be aware that data or additional configuration information might be accepted on multiple ports. The user must exercise care to insure that the incoming configuration and data does not interfere with the device programming. In many cases, a partial reset may clear unwanted data, but may cause corruption of active transfers. Before operation, the SerB must be configured. The steps of configuration are as follows: Power on. No power sequencing is required, but all power supplies must have achieved the minimum required level before proceeding. Master reset may be applied at any time. If reset is performed in association with Power on, reset may be applied before, during or after Power On, but the reset must be held after achieving valid power levels for the designated minimum number of clock cycles (defined in the electrical section). SerB will initialize itself according to the hard-wired pins. - The PLLs will take time to lock - The PHYs will begin to negotiate with neighboring devices, attempting to establish links - The memory will be allocated, per the default configuration I2C may be used for additional programming if required without waiting for PLL lock. All of the configuration registers may be programmed through I2C. JTAG has access to the configuration registers. If JTAG is not used for additional programming, the JTAG inputs should be disabled. Full operation of JTAG is described in the JTAG section. In the event that the SerB needs to be programmed over a serial port, the serial port must have achieved full Link Up status before programming may commence. If interrupt masks are needed, the masks should be programmed using one of the programming methods. After programming, the SerB should be fully functional. It should be noted that the SerB may be reconfigured at any time. It should be noted that at any time, the SerB may reconfigured through I2C or a Serial Port.
9.5 Initialization of RIO Ports
The sRIO ports shall be initialized before they are operational. More needs to be developed on this topic, but as a start, the following references should be made: PPS specification an sRIO port Initialization RIO Physical Layer Specification section 4.6 RIO System Bring-up document for explanation and examples of system bring-up Hard-wired pin description The initialization of the sRIO ports may be influenced by the following sources: sRIO maintenance packets I2C programming JTAG programming Hard-wired inputs
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10.0 Reference Clock
There are several clocks associated with the SerB. All internal operational clocks within the SerB are generated from the PHY Reference clock operating at 156.25M Hz. The following clocks are used within the SerB: 1. 2. 3. PHY Reference Clock. This clock is an input at 156.25M Hz and is used to drive the serial ports and internal functions. When P-Port is a QDR memory port, the PHY Reference clock also drives the memory interface. JTAG Clock I2C Clock
10.1 Reference Clock Electrical Specifications
The reference clock is 156.25 MHz, and is AC-coupled with the following electrical specifications:
LI, CLK REF_CLK_P CI, CLK RL,CLK
+
REF_CLK
VBIAS, CLK LI, CLK RL,CLK
-
REF_CLK_N CI, CLK
5686 drw07
Figure 12 REF_CLK representative circuit
Name
REF_CLK tDUTY_REF tRCLK/tFCLK vIN_CML RL_CLK LI_CLK CI_CLK
Description
REF_CLK clock running at 156.25Mhz REF_CLK duty cycle Input signal rise/fall time (20%-80%) Differential peak-peak REF_CLK input swing Input termination resistance Input inductance Input capacitance
Min
-100 40 200 400 40
---------
Nom
----
Max
+100 60 650 2400 60 4 5
Units
ppm % ps mV ohm nH pF
50 500
----
50
---------
Table 96 Input Reference Clock Jitter Specifications
The reference clock wander should not be more than 100ppm (for 156.25 Mhz, this is +/-15.625 KHz). This requirement comes from the sRIO specification that outgoing signals from separate links, which belong to the same port, should not be separated more than 100ppm. Note that the series capacitors are descretes that must be placed external to the devices's receivers. All other elements are associated with the input structure internal to the device. VBIAS is generated internally.
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11.0 Absolute Maximum Ratings(1)
Symbol
VTERM (VDD3) VTERM(2) (VDD3-supplied interfaces) VTERM (VDD) VTERM(2) (VDD-supplied interfaces) VTERM (VDDS) VTERM(2) (VDDS-supplied interfaces) VTERM (VDDA) VTERM(2) (VDDA-supplied interfaces) TBIAS(3) TSTG TJN IOUT (For VDD3 = 3.3V) IOUT (For VDD3 = 2.5V)
Rating
VDD3 Terminal Voltage with Respect to GND Input or I/O Terminal Voltage with Respect to GND VDD Terminal Voltage with Respect to GND Input or I/O Terminal Voltage with Respect to GND VDDS Terminal Voltage with Respect to GNDS Input or I/O Terminal Voltage with Respect to GNDS VDDA Terminal Voltage with Respect to GNDS Input or I/O Terminal Voltage with Respect to GNDS Temperature Under Bias Storage Temperature Junction Temperature DC Output Current DC Output Current
Commercial & Industrial
-0.5 to 3.6 -0.3 to VDD3+0.3
Unit
V V
-0.5 to 1.5 -0.3 to VDD+0.3
V V
-0.5 to 1.5 -0.3 to VDDS+0.3
V V
-0.5 to 1.5 -0.3 to VDDA+0.3
V V
-55 to +125 -65 to +150 +150 30 30
C C C mA mA
Table 97 Absolute Maximum Ratings
Note: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any Input or I/O pin cannot exceed its corresponding supply voltage during power supply ramp up. Ambient Temperature under DC Bias. No AC Conditions.
2.
3.
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11.1 Recommended Temperature and Operating Voltage1
Grade Ambient Temperature
0C to 70'C
Max Junction Temperature (TJN)
125C
Ground(2)
GND = 0V GNDS = 0V
Supply Voltage(4)
VDD = 1.2 +/- 5% VDDQ = 1.5 +/- 5% VDDS = 1.2 +/- 5% VDD3(3) = 3.3 +/- 5%, or 2.5V +/- 100mV VDDA = 1.2 +/- 5%
Commercial
Industrial
-40C to 85C
125'C
GND = 0V GNDS = 0V
VDD = 1.2 +/- 5% VDDQ = 1.5 +/- 5% VDDS = 1.2 +/- 5% VDD3(3) = 3.3 +/- 5%, or 2.5V +/- 100mV VDDA = 1.2 +/- 5%
Table 98 Recommended Temperature and Operating Voltage
Note: 1. Power sequencing is not necessary; however, the voltage on any Input or I/O pin cannot exceed its corresponding supply voltage during power supply ramp up. The device is not sensitive to supply rise and fall times, and thus these are not specified. VDD3, VDDA, and VDDS share a common ground (GNDS). Core supply and ground are VDD and GND respectively. VDD3 may be operated at either 3.3V or 2.5V simply by providing that supply voltage. For those interfaces operating on this supply, this datasheet provides input and output specifications at each of these voltages. VDDS & VDDA may be tied to a common plane. VDD (core, digital supply) should have its own supply and plane.
2. 3. 4.
11.2 AC Test Conditions
Input Pulse Levels
Input Rise / Fall Times Input Timing Reference Levels Output Reference Levels Output Load
GND to 3.0V / GND to 2.4V
2ns 1.5V / 2.5V 1.5V / 1.25V Figure 12
Table 99 AC Test Conditions (VDD3 = 3.3V / 2.5V): JTAG, I2C, RST
Figure 13 AC Output Test Load (JTAG)
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Figure 14 AC Output Test Load (I2C)
Note: 1. The SDA and SCL pins are open-drain drivers. Refer to the Philips I2C Specification [1] for appropriate selection of pull-up resistors for each.
Figure 15 sRIO Lanes Test Load
Note: 1. The characteristic impedance Z0 should be designed for 100 ohms. An in line capacitor C1 and C2 at each input of the receiver provides AC-coupling and a DC-block. The IST recommended and test value is 100nF for each. Thus, ant DC bias differential between the two devices on the link is negated. The differential input resistance is designed to be 100 Ohms (per sRIO specification). Thus, R1 and R2 are 50 Ohms each. Note that VBIAS is the internal bias voltage of the device's receiver.
11.3 Typical Power Figures
Typical Power Draw 4.5W (all supplies)
IDD 2.0A
IDDS 460mA
IDDA 216mA
IDDQ 465mA
IDD3 30mA
Table 100 Typical Power Figures
Note: 1. Values are based on characterization, and are not production tested.
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12.0 I2C-Bus
The SerB is compliant with the I2C specification [1]. This specification provides all functional detail and electrical specifications associated with the I2C bus. This includes signaling, addressing, arbitration, AC timing, DC specifications, and other details. The I2C bus is comprised of Serial Data (SDA) and Serial Clock (SCL) pins and can be used to attach a CPU for initialization and management purposes. A CPU can then access registers and program the device, but it cannot access other devices attached to the sRIO interfaces through the I2C bus. The I2C interface supports Fast/Standard (F/S) mode (400/ 100 kHz). The SerB does NOT support CBUS or General Address calls.
12.1 I2C Device Address
Relative to I2C, the SerB is a slave-only receiver and transmitter. The device address for the SerB is fully pin-defined by 10 external pins. This provides full flexibility in defining the slave address to avoid conflicting with other I2C devices on a given bus. The SerB may be operated as either a 10-bit addressable device or a 7-bit addressable device based on another external pin Address Select (ADS). If the ADS pin is tied to Vdd, then the SerB operates as a 10-bit addressable device and the device address will be defined as ID[9:0]. If the ADS pin is tied to GND, then the SerB operates as a 7-bit addressable device with the device address defined by ID[6:0]. The addressing mode must be established at power-up and remain static throughout operation. Dynamic changes will result in undetermined behavior.
Pin
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9
I2C Address Bit (pin_addr)
0 1 2 3 4 5 6 7 (don't care in 7-bit mode) 8 (don't care in 7-bit mode) 9 (don't care in 7-bit mode)
Table 101 I2C static address selection pin configuration
All of the SerB's registers are addressable through I2C. These registers are accessed via 22-bit addresses and 32-bit word boundaries though standard reads and writes. These registers may also be accessed through the sRIO and JTAG interfaces.
12.2 Signaling
The SerB is a slave-only receive and transmit device. Thus, communication with the SerB on the I2C bus follows these two cases: 1. Suppose a master device wants to send information to the SerB: - Master device addresses SerB (slave) - Master device (master-transmitter), sends data to SerB (slave- receiver) - Master device terminates the transfer If a master device wants to receive information from the SerB: - Master device addresses SerB (slave) - Master device (master-receiver) receives data from SerB (slave- transmitter) - Master device terminates the transfer.
2.
All signaling is fully compliant with I2C. Full detail of signaling can be found in the I2C specification [1].
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12.2.1 Interfacing to Standard-, Fast-, and Hs-mode devices The SerB supports Fast / Standard (F/S) modes of operation. Per I2C specification, in mixed speed communication the SerB supports Hs- and Fast-mode devices at 400 kbit/s, and Standard-mode devices at 100 kbit/s. Please refer to the I2C specification for detail on speed negotiation on a mixed speed bus. 12.2.2 SerB Specific Memory Access There is a SerB-specific I2C memory access implementation. This implementation is fully I2C compliant. It requires the memory address to be explicitly specified during writes. This provides directed memory accesses through the I2C bus. Subsequent reads always begin at the address specified during the last write. The write procedure requires the 3-Bytes (22-bits) of memory address to be provided following the device address. Thus, the following are required: device address - one or two bytes depending on 10-bit/7-bit addressing, memory address - 3 bytes yielding 22-bits of memory address, and a 32-bit data payload - 4 byte words. The read procedure has the memory address section of the transfer removed. Thus, to perform a read, the proper access would be to perform a write operation and issue a repeated start after the acknowledge bit following the third byte of memory address. Then, the master would issue a read command selecting the SerB through the standard device address procedure with the R/W bit high. Note that in 10-bit device address mode (ADS=1), only the two MSBs need be provided during this read. Data from the previously loaded address would immediately follow the device address protocol. It is possible to issue a stop or repeated start anytime during the write data payload procedure, but must be before the final acknowledge (i.e. canceling the write before the actual write operation is completed and performed). Also, the master would be allowed to access other devices attached to the I2C bus before returning to select the SerB for the subsequent read operation from the loaded address.
12.3 Figures
R/W Bit (R=1, W=0) Data output is from base mem_addr[21:0]
8 1110 1A
Device Address [9:8] Data Word #1 MSB Byte
17 A
Data Word #1 Byte #2
26 A
Data Word #1 Byte #3
35 A
Data Word #1 LSB Byte
44 A
5686 drw05
Figure 16 Write protocol with 10-bit Slave Address (ADS =1)
Note: 1. I2C writes to memory align on 32-bit word boundaries, thus the 22 address MSBs must be provided while the 2 LSBs associated with word and byte pointers are DON'T CARE and are therefore not transmitted.
R/W Bit (R=1, W=0) Data output is from base mem_addr[21:0] 8 1110 1A Data Word #1 MSB Byte 17 A Data Word #1 Byte #2 26 A Data Word #1 Byte #3 35 A Data Word #1 LSB Byte 44 A
Device Address [9:8]
Figure 17 Read Protocol with 10-bit Slave Address (ADS=1)
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R/W Bit (R=1, W=0) Data output is from base mem_addr[21:0]
8 1A
Device Address [6:0] Data Word #1 MSB Byte
17 A
Data Word #1 Byte #2
26 A
Data Word #1 Byte #3
35 A
Data Word #1 LSB Byte
5686 drw06
Figure 18 Write protocol with 7-bit Slave Address (ADS=0)
Note: 1. I2C writes to memory align on 32-bit word boundaries, thus the 22 address MSBs must be provided while the 2 LSBs associated with word and byte pointers are DON'T CARE and are therefore not transmitted.
R/W Bit (R=1, W=0) 8 1A Device Address [6:0] Data Word #1 MSB Byte 17 A
Data output is from base mem_addr[21:0] 26 A Data Word #1 Byte #2 Data Word #1 Byte #3 35 A Data Word #1 LSB Byte
Figure 19 Read protocol with 7-bit Slave Address (ADS=0)
12.4 I2C DC Electrical Specifications
Note that the ADS and ID pins will all run off the core (1.2V) power supply, and these pins are required to be fixed during operation. Thus, these pins must be statically tied to the 1.2V supply or GND. Tables 19 and 20 below lists the SDA and SCL electrical specifications for F/S-mode I2C devices: At recommended operating conditions with VDD3 = 3.3V 5%
Figure 20 I2C SDA & SCL DC Electrical Specifications
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At recommended operating conditions with VDD3 = 2.5V 100mV
Figure 21 I2C SDA & SCL DC Electrical Specifications
12.5 I2C AC Electrical Specifications
Figure 22 Specifications of the SDA and SCL bus lines for F/S-mode I2C -bus devices
Note: 1. 2. 3. 4. For more information, see the I2C-Bus specification by Philips Semiconductor [1]. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT > 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released.
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12.6 I2C Timing Waveforms
Figure 23 I2C Timing Waveforms
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13.0 Serial RapidIOTM AC Specifications
13.1 Overview
The SerB's SERDES are in full compliance to the RapidIOTM AC specifications for the LP-Serial physical layer [5]. This section provides those specifications for reference. The electrical specifications cover both single and multiple-lane links. Two transmitters (short run and long run) and a single receiver are specified for each of three baud rates, 1.25, 2.50, and 3.125 GBaud. Two transmitter specifications allow for solutions ranging from chip-to-chip interconnect to driving two connectors across a backplane. A single receiver specification is given that will accept signals from both the short run and long run transmitter specifications. The short run transmitter should be used mainly for chip-to-chip connections on either the same printed circuit board or across a single connector. This covers the case where connections are made to a mezzanine (daughter) card. The minimum swings of the short run specification reduce the overall power used by the transceivers. The long run transmitter specifications use larger voltage swings that are capable of driving signals across backplanes. This allows a user to drive signals across two connectors and a backplane. The SerB can drive beyond the specification distance of at least 50 cm at all baud rates. Please use IDT's Simulation Kit IO models to determine reach and signal quality for a given PCB design. All unit intervals are specified with a tolerance of +/- 100 ppm. The worst case frequency difference between any transmit and receive clock will be 200 ppm. To ensure inter-operability between drivers and receivers of different vendors and technologies, AC coupling at the receiver input must be used.
13.2 Signal Definitions
LP-Serial links uses differential signaling. This section defines terms used in the description and specification of differential signals. Differential Peak-Peak Voltage of Transmitter or Receiver shows how the signals are defined. The figure below shows waveforms for either a transmitter output (TD and TD) or a receiver input (RD and RD). Each signal swings between A Volts and B Volts where A > B. Using these waveforms, the definitions are as follows: 1. 2. 3. 4. 5. 6. 7. The transmitter output signals and the receiver input signals TD,TD, RD and RD each have a peak-to-peak swing of A - B Volts The differential output signal of the transmitter, VOD, is defined as VTD-VTD. The differential input signal of the receiver, VID, is defined as VRD-VRD. The differential output signal of the transmitter and the differential input signal of the receiver each range from A - B to -(A - B) Volts. The peak value of the differential transmitter output signal and the differential receiver input signal is A - B Volts The peak-to-peak value of the differential transmitter output signal and the Differential receiver input signal is 2 * (A - B) Volts
Figure 24 Differential Peak-Peak Voltage of Transmitter or Receiver
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To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5V and 2.0V. Using these values, the peak-to-peak voltage swing of the signals TD and TD is 500 mV p-p. The differential output signal ranges between 500 mV and -500 mV. The peak differential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mV pp.
13.3 Equalization
With the use of high speed serial links, the interconnect media will cause degradation of the signal at the receiver. Effects such as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss can be large enough to degrade the eye opening at the receiver beyond what is allowed in the specification. To negate a portion of these effects, equalization can be used. The equalization technique implemented in the SerB is Pre-emphasis on the transmitter (under register control)
13.4 Explanatory Note on Transmitter and Receiver Specifications
AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at three baud rates (a total of six cases) are described. The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified in Clause 47 of IEEE 802.3ae-2002. XAUI has similar application goals to serial RapidIOTM. The goal of this standard is that electrical designs for serial RapidIOTM can reuse electrical designs for XAUI, suitably modified for applications at the baud intervals and reaches described herein.
13.5 Transmitter Specifications
LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section. The differential return loss, S11, of the transmitter in each case shall be better than -10 dB for (Baud Frequency)/10 < Freq(f) < 625 MHz, and -10 dB + 10log(f/625 MHz) dB for 625 MHz <= Freq(f) <= Baud Frequency The reference impedance for the differential return loss measurements is 100 Ohm resistive. Differential return loss includes contributions from on-chip circuitry, chip packaging and any off-chip components related to the driver. The output impedance requirement applies to all valid output levels. The 80KSBR200 satisfies the specification requirement that the 20%-80% rise/fall time of the transmitter, as measured at the transmitter output, in each case have a minimum value 60 ps. Similarly the timing skew at the output of an LP-Serial transmitter between the two signals that comprise a differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50 GB and 15 ps at 3.125 GB.
Figure 25 Short Run Transmitter AC Timing Specifications - 1.25 GBaud
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Figure 26 Short Run Transmitter AC Timing Specifications - 2.5 GBaud
Figure 27 Short Run Transmitter AC Timing Specifications - 3.125 GBaud
Figure 28 Long Run Transmitter AC Timing Specifications - 1.25 GBaud
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Figure 29 Long Run Transmitter AC Timing Specifications - 2.5 GBaud
Figure 30 Long Run Transmitter AC Timing Specifications - 3.125 GBaud
For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the transmitter shall fall entirely within the un-shaded portion of the Transmitter Output Compliance Mask shown in Figure 30 with the parameters specified in Figure 31. The eye pattern is measured at the output pins of the device and the device is driving a 100 Ohm +/- 5% differential resistive load. The output eye pattern of a LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol interference) need only comply with the Transmitter Output Compliance Mask when pre-emphasis is disabled or minimized.
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Figure 31 Transmitter Output Compliance Mask
Figure 32 Transmitter Differential Output Eye Diagram Parameters
13.6 Receiver Specifications
LP-Serial receiver electrical and timing specifications are stated in the text and tables of this section. Receiver input impedance shall result in a differential return loss better that 10 dB and a common mode return loss better than 6 dB from 100 MHz to (0.8)*(Baud Frequency). This includes contributions from on-chip circuitry, the chip package and any off-chip components related to the receiver. AC coupling components are included in this requirement. The reference impedance for return loss measurements is 100 Ohm resistive for differential return loss and 25 Ohm resistive for common mode.
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Figure 33 Receiver AC Timing Specifications - 1.25 GBaud
Note: 1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the un-shaded region of Figure 35. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects
Figure 34 Receiver AC Timing Specifications - 2.5 GBaud
Note: 1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the un-shaded region of Figure 35. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
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Figure 35 Receiver AC Timing Specifications - 3.125 GBaud
Note: 1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the un-shaded region of Figure 35. The sinusoidal jitter component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
Figure 36 Single Frequency Sinusoidal Jitter Limits
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13.6.1 Receiver Eye Diagrams For each baud rate at which an LP-Serial receiver is specified to operate, the receiver meets the corresponding Bit Error Rate specification (Receiver AC Timing Specification - 1.25 GBaud, Receiver AC Timing Specification - 2.5 GBaud, and Receiver AC Timing Specification - 3.125 GBaud) when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter) falls entirely within the un-shaded portion of the Receiver Input Compliance Mask shown in Figure 36 with the parameters specified in Figure 37. The eye pattern of the receiver test signal is measured at the input pins of the receiving device with the device replaced with a 100 Ohm +/- 5% differential resistive load.
Figure 37 Receiver Input Compliance Mask
Figure 38 Receiver Input Compliance Mask Parameters exclusive of Sinusoidal Jitter
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14.0 Parallel Port Electrical Characteristics
The parallel port on the SerB can connect to a QDRII-B4 x36 SRAM. The SerB acts as a memory controller and drives the external SRAM. The P-Port may also be disabled. The electrical requirements of the P-Port are simply must be QDRII compatible. As a FIFO controller, the SerB must be Burst 4 compatible. Included in the Parallel Port Requirements is the need for programmable output impedance as is used in the QDRII SRAM. This includes the attachment of an external resistor to set the impedance. The Serial interface operate at 3.125G bps with 8B/10B encoding on each lane. After decoding and alignment of the four lanes, the maximum data rate is 10G bps across the interface in each direction. The external memories are all burst of four. The clock rate on the bus is specified at 156.25 MHz. The 156.25 MHz is sufficient to support the 10G bps total bandwidth in each direction necessary on the P-Port. Please refer to figure below for SerB to external QDRII SRAM interface connections.
Serial Buffer P-Port
Address(23) K, K# (center) Wr# Rd# D(36) Q(36) CQ, CQ# (edge)
QDR2 SRAM SA K, K# Wr# Rd# D(36) Q(36) CQ, CQ# C/ C# BW(4)
Figure 39 P-Port Signals Connected to a QDRII SRAM
14.1 AC Electrical Characteristics
In this mode, the P-Port electrical characteristics and interface shall be fully compliant with designated QDRII SRAM devices at HSTL levels. While QDRII has the ability to operate at 1.8V and other voltages in between 1.8V and HSTL, there is no requirement for the SerB to operate beyond HSTL. There will be a direct connection from the P-Port to the memory. The drive requirements of the interface will be HSTL Class 1 or less. There is a ZQ pin for setting interface impedance. When connected to a QDR memory, the specific needs of the QDRII device must be met. The P-Port to QDR SRAM clocking include the following: The P-Port output clock / QDR input clock shall be center aligned and designed to clock the QDRII SRAM K/ K# input clock. The P-Port input clock shall be edge aligned and designed to connect to the CQ/CQ# output of the QDRII SRAM. It is strongly suggested that the C/C# clocks not be returned to the SerB P-Port. The SerBs PHY clock is used internally to generate the P-Port output clock Please refer to table below for specific AC Electrical Characteristics requirements.
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156.25MHz Symbol Clock Parameters tKHKH tKC var tKHKL tKLKH tKHKH tKHKH tKHCH tCK lock tKC reset Clock Cycle Time (K,K,C,C) Clock Phase Jitter (K,K,C,C) Clock High Time (K,K,C,C) Clock Low Time (K,K,C,C) Clock to clock (K K,C C) Clock to clock (K K,C C) Clock to data clock (K C,K C) DLL lock tim (K, C) K static to DLL reset 6.00 2.40 2.40 2.70 2.70 0.00 1024 30 8.40 0.20 2.80 ns ns ns ns ns ns ns cycles ns 2 1 5 5 6 6 Parameter Min. Max. Unit Notes
Output Parameters tCHQV tCHQX tCHCQV tCHCQX tCQHQV tCQHQX tCHQZ tCHQX1 Set-Up Times tAVKH tIVKH tDVKH Hold Times tKHAX tKHIX tKHDX K, K rising edge to address hold K, K rising edge to R, W inputs hold K, K rising edge to data-in hold 0.50 0.50 0.50 ns ns ns 6 Address valid to K, K rising edge R, W inputs valid to K, K rising edge Data-in valid to K, K rising edge 0.50 0.50 0.50 ns ns ns 4 C, C HIGH to output valid C, C HIGH to output hold C, C HIGH to echo clock valid C, C HIGH to echo clock hold CQ, CQ HIGH to output valid CQ, CQ HIGH to output hold C HIGH to output High-Z C HIGH to output Low-Z -0.50 -0.50 -0.40 -0.50 0.50 0.50 0.40 0.50 ns ns ns ns ns ns ns ns 3 3 3 3 3 3
Table 102 AC Electrical Characteristics
Note: 1. 2. 3. 4. 5. 6. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. Vdd slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable. If C, C are tied High, K, K become the references for C, C timing parameters. All address inputs must meet the specified setup and hold times for all latching clock edges. Clock High time (tKHKL) and Clock Low time (tKLKH) should be within 40% to 60% of the duty cycle time (tKHKH). Clock to Clock time (tKHKH) and Clock to Clock time (tKHKH) should be within 45% to 55% of the duty cycle time (tKHKH).
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Read A0 1
W rite A1 2
Read A2 3
W rite A3 4
Read A 4 5
W rite A5 6
N OP 7
W rite A 6 8
NO P 9
NO P 10
K
tKHKL tKLKH tKHKH tKHKH
K
R
tIV KH tKHIX
W
SA
A0
A1
A2
A3
A4
A5
A6
tAVK H tKHAX
tAVKH tKHAX
D
D10
D11
D30
D 31
D50
D51
D60
D61
tDVK H tK HDX
tD VKH tKHDX
Q
tC HQ X1
Q00
Q 01
Q 20
Q 21
Q 40
Q 41
tCHQ Z
tC HQX tK HCH tK LK H tC HQV
tC HQ X tC HQV
tC QH QV
tC Q H Q X
C
tKH KL tK HCH tKH KH tK HKH
C
tCHC QV tCH CQ X
CQ
tC HCQV tCH CQ X
CQ
6 109 d rw 09 a
Figure 40 Timing Waveform of Combined Read and Write Cycles
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15.0 JTAG Interface
The 80KSBR200 offers full JTAG (Boundary Scan) support for both its slow speed and high speed pins. This allows "pins-down" testing of newly manufactured printed circuit boards as well as troubleshooting of field returns. The JTAG TAP interface also offers an alternative method for Configuration Register Access (CRA) (along with the sRIO and I2C ports). Thus this port may be used for programming the SerB's many registers. Boundary scan testing of the AC-coupled IOs is performed in accordance with IEEE 1149.6 (AC Extest).
15.1 IEEE 1149.1 (JTAG) & IEEE 1149.6 (AC Extest) Compliance
All DC pins are in full compliance with IEEE 1149.1 [10]. All AC-coupled pins fully comply with IEEE 1149.6 [11]. All 1149.1 and 1149.6 boundary scan cells are on the same chain. No additional control cells are provided for independent selection of negative and/or positive terminals of the TX- or RX-pairs.
15.2 System Logic TAP Controller Overview
The system logic utilizes a 16-state, six-bit TAP controller, a four-bit instruction register, and five dedicated pins to perform a variety of functions. The primary use of the JTAG TAP Controller state machine is to allow the five external JTAG control pins to control and access the SerB's many external signal pins. The JTAG TAP Controller can also be used for identifying the device part number. The JTAG logic of the 80KSBR200 is depicted in the figure below.
Boundary Scan Register Device ID Register Bypass Register Instruction Register Decoder TDI TMS TCK Tap Controller m u x m u x
TDO
4-Bit Instruction Register
TRST
Figure 41 Diagram of the JTAG Logic
15.3 Signal Definitions
JTAG operations such as Reset, State-transition control and Clock sampling are handled through the signals listed in the table below. A functional overview of the TAP Controller and Boundary Scan registers is provided in the sections following the table.
Pin Name
TRST TCK
Type
Input Input
Description
JTAG RESET Asynchronous reset for JTAG TAP controller (internal pull-up) JTAG Clock Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge. JTAG_TDO is output on the falling edge. JTAG Mode Select. Requires an external pull-up. Controls the state transitions for the TAP controller state machine (internal pull-up)
TMS
Input
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TDI
Notes
Type
Input
Description
JTAG Input Serial data input for BSC chain, Instruction Register, IDCODE register, and BYPASS register (internal pull-up) JTAG Output Serial data out. Tri-stated except when shifting while in Shift-DR and SHIFT-IR TAP controller states.
TDO
Output
Table 103 JTAG Pin Descriptions (Part 2 of 2)
The system logic TAP controller transitions from state to state, according to the value present on JTMS, as sampled on the rising edge of TCK. The Test-Logic Reset state can be reached either by asserting TRST or by applying a 1 to TMS for five consecutive cycles of TCK. A state diagram for the TAP controller appears in Figure 41. The value next to state represent the value that must be applied to TMS on the next rising edge of TCK, to transition in the direction of the associated arrow.
1 0
Test- Logic Reset
0
Run-Test/ Idle
1 1
SelectDR-Scan
1
SelectIR-Scan
0 1 Capture-DR 0
Shift-DR
1 0
0
Capture-IR
0
Shift-IR
0
1
Exit1 -DR
1 1 0
Exit1-IR
1 0 0
0
Pause-DR
Pause-IR
1 0 Exit2-DR 1
Update-DR
1 0
Exit2-IR
1
Update-IR
0
1
0
1
0
Figure 42 State Diagram of the 80KSBR200's TAP Controller
15.4 Test Data Register (DR)
The Test Data register contains the following: The Bypass register The Boundary Scan registers The Device ID register These registers are connected in parallel between a common serial input and a common serial data output, and are described in the following sections. For more detailed descriptions, refer to IEEE Standard Test Access port (IEEE Std. 1149.1-1990).
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15.4.1 Boundary Scan Registers The 80KSBR200 boundary scan chain is 140 bits long. The five JTAG pins do not have scan elements associated with them. Full boundary scan details can be found in the associated BSDL file which may be found on our web site (www.IDT.com). The boundary scan chain is connected between TDI and TDO when the EXTEST or SAMPLE/PRELOAD instructions are selected. Once EXTEST is selected and the TAP controller passes through the UPDATE-IR state, whatever value that is currently held in the boundary scan register's output latches is immediately transferred to the corresponding outputs or output enables. Therefore, the SAMPLE/PRELOAD instruction must first be used to load suitable values into the boundary scan cells, so that inappropriate values are not driven out onto the system pins. All of the boundary scan cells feature a negative edge latch, which guarantees that clock skew cannot cause incorrect data to be latched into a cell. The input cells are sampleonly cells. The simplified logic configuration is shown in the figure below.
Input Pin
To core logic
MUX
From previous cell
D
Q
To next cell
shift_dr
clock_dr
Figure 43 Diagram of Observe-only Input Cell
The simplified logic configuration of the output cells is shown in the figure below.
EXTEST Data from Core MUX To Output Pad To Next Cell
MUX
D
Q
D
Q
Data from Previous Cell shift_dr
clock_dr
update_dr
Figure 44 Diagram of Output Cell
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The output enable cells are also output cells. The simplified logic appears in the figure below.
EXTEST Output Enable From Core MUX To output enable To next cell
MUX
Data from previous cell shift_dr
D
Q
D
Q
clock_dr
update_dr
Figure 45 Diagram of Output Enable Cell
The bidirectional cells are composed of only two boundary scan cells. They contain one output enable cell and one capture cell, which contains only one register. The input to this single register is selected via a mux that is selected by the output enable cell when EXTEST is disabled. When the Output Enable Cell is driving a high out to the pad (which enables the pad for output) and EXTEST is disabled, the Capture Cell will be configured to capture output data from the core to the pad. However, in the case where the Output Enable Cell is low (signifying a tri-state condition at the pad) or EXTEST is enabled, the Capture Cell will capture input data from the pad to the core. The configuration is shown graphically in the figure below.
From previous cell Output enable from core Output Enable Cell EXTEST
Output from core Input to core
MUX
Capture Cell
I/O Pin
To next cell
Figure 46 Diagram of Bidirectional Cell
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15.5 Instruction Register (IR)
The Instruction register allows an instruction to be shifted serially into the SerB at the rising edge of TCK. The instruction is then used to select the test to be performed or the test register to be accessed, or both. The instruction shifted into the register is latched at the completion of the shifting process, when the TAP controller is at the Update-IR state. The Instruction Register contains four shift-register-based cells that can hold instruction data. This register is decoded to perform the following functions: To select test data registers that may operate while the instruction is current. The other test data registers should not interfere with chip operation and selected data registers. To define the serial test data register path used to shift data between TDI and TDO during data register scanning. The Instruction Register is comprised of 4 bits to decode instructions, as shown in the table below.
Instruction
EXTEST
Definition
Mandatory instruction allowing the testing of board level interconnections. Data is typically loaded onto the latched parallel outputs of the boundary scan shift register using the SAMPLE/PRELOAD instruction prior to use of the EXTEST instruction. EXTEST will then hold these values on the outputs while being executed. Also see the CLAMP instruction for similar capability. Mandatory instruction that allows data values to be loaded onto the latched parallel output of the boundary-scan shift register prior to selection of the other boundary-scan test instruction. The Sample instruction allows a snapshot of data flowing from the system pins to the on-chip logic or vice versa. Provided to select Device Identification to read out manufacturer's identity, part, and version number. Tri-states all output and bidirectional boundary scan cells. Provides JTAG user the option to bypass the part's JTAG controller while keeping the part outputs controlled similar to EXTEST. AC Extest instruction implemented in accordance with the requirements of the IEEE std. 1149.6 specification. AC Extest instruction implemented in accordance with the requirements of the IEEE std. 1149.6 specification. Behaviorally equivalent to the BYPASS instruction as per the IEEE std. 1149.1 specification. However, the user is advised to use the explicit BYPASS instruction. SerB-specific opcode to allow reading and writing of the configuration registers. Reads and writes must be 32-bits. See further detail below. For internal use only. Do not use. To shift the internal fuse status out to TDO pin. For internal use only. Do not use. The BYPASS instruction is used to truncate the boundary scan register as a single bit in length.
OPcode [3:0]
0000
SAMPLE/ PRELOAD
0001
IDCODE HIGHZ CLAMP EXTEST_PULSE EXTEST_TRAIN RESERVED CONFIGURATION REGISTER ACCESS (CRA) PRIVATE SHIFT FUSE STATUS PRIVATE BYPASS
0010 0011 0100 0101 0110 0111 -- 1001 1010
1011 -- 1100 1101 1110 1111
Table 104 Instructions Supported By 80KSBR200's JTAG Boundary Scan
15.5.1 EXTEST The external test (EXTEST) instruction is used to control the boundary scan register, once it has been initialized using the SAMPLE/PRELOAD instruction. Using EXTEST, the user can then sample inputs from or load values onto the external pins of the 80KSBR200. Once this instruction is selected, the user then uses the SHIFT-DR TAP controller state to shift values into the boundary scan chain. When the TAP controller passes through the UPDATE-DR state, these values will be latched onto the output pins or into the output enables.
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Advanced Datasheet*
Notes
15.5.2 SAMPLE/PRELOAD The sample/preload instruction has a dual use. The primary use of this instruction is for pre-loading the boundary scan register prior to enabling the EXTEST instruction. Failure to preload will result in unknown random data being driven onto the output pins when EXTEST is selected. The secondary function of SAMPLE/PRELOAD is for sampling the system state at a particular moment. Using the SAMPLE function, the user can halt the device at a certain state and shift out the status of all of the pins and output enables at that time. 15.5.3 BYPASS The BYPASS instruction is used to truncate the boundary scan register to a single bit in length. During system level use of the JTAG, the boundary scan chains of all the devices on the board are connected in series. In order to facilitate rapid testing of a given device, all other devices are put into BYPASS mode. Therefore, instead of having to shift 140 times to get a value through the 80KSBR200, the user only needs to shift one time to get the value from TDI to TDO. When the TAP controller passes through the CAPTURE-DR state, the value in the BYPASS register is updated to be 0. If the device being used does not have an IDCODE register, then the BYPASS instruction will automatically be selected into the instruction register whenever the TAP controller is reset. Therefore, the first value that will be shifted out of a device without an IDCODE register is always 0. Devices such as the 80KSBR200 that include an IDCODE register will automatically load the IDCODE instruction when the TAP controller is reset, and they will shift out an initial value of 1. This is done to allow the user to easily distinguish between devices having IDCODE registers and those that do not. 15.5.4 CLAMP This instruction, listed as optional in the IEEE 1149.1 JTAG Specifications, allows the boundary scan chain outputs to be clamped to fixed values. When the clamp instruction is issued, the scan chain will bypass the 80KSBR200 and pass through to devices further down the scan chain. 15.5.5 IDCODE The IDCODE instruction is automatically loaded when the TAP controller state machine is reset either by the use of the TRST signal or by the application of a `1' on TMS for five or more cycles of TCK as per the IEEE Std 1149.1 specification. The least significant bit of this value must always be 1. Therefore, if a device has a IDCODE register, it will shift out a 1 on the first shift if it is brought directly to the SHIFT-DR TAP controller state after the TAP controller is reset. The board- level tester can then examine this bit and determine if the device contains a DEVICE_ID register (the first bit is a 1), or if the device only contains a BYPASS register (the first bit is 0). However, even if the device contains an IDCODE register, it must also contain a BYPASS register. The only difference is that the BYPASS register will not be the default register selected during the TAP controller reset. When the IDCODE instruction is active and the TAP controller is in the Shift-DR state, the thirty-two bit value that will be shifted out of the device-ID register is 0x004F0037.
Bit(s)
0 11:1 27:12
Mnemonic
reserved Manuf_ID Part_number reserved 0x1
Description
R/W
R R R
Reset
1 0x033 impl. dep. impl. dep.
Manufacturer Identity (11 bits) IDT 0x33 Part Number (16 bits) This field identifies the part number of the processor derivative. For the 80KSBR200 this value is: 0x04F0 Version (4 bits) This field identifies the version number of the processor derivative. For the 80KSBR200, this value is 0x0
31:28
Version
R
Table 105 System Controller Device Identification Register
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IDT 80KSBR200
Advanced Datasheet*
Notes
Version
0000
Part Number
0000|0100|1111|0000
Manuf ID
0000|0011|011
LSB
1
Figure 106 System Controller Device ID Instruction Format
15.5.6 EXTEST PULSE This IEEE 1149.6 instruction applies only to the AC-coupled pins. All DC pins will perform as if the IEEE Std 1149.1 EXTEST instruction is operating whenever the EXTEST_PULSE instruction is effective. The EXTEST_PULSE instruction enables edge-detecting behavior on signal paths containing AC pins, where test receivers reconstruct the original waveform created by a driver even when signals decay due to AC-coupling. As the operation name suggests, enabling EXTEST_PULSE causes a pulse to be issued which can be detected even on AC-coupled receivers. Refer to the IEEE Std 1149.6 for full details. Below is a short synopsis. If enabled, the output signal is forced to the value in its associated Boundary-Scan Register data cell for its driver (true and inverted values for a differential pair) at the falling edge of TCK in the Update-IR and Update-DR TAP Controller states. The output subsequently transitions to the opposite of that state (an inverted state) on the first falling edge of TCK that occurs after entering the Run-Test/Idle TAP Controller state. It then transitions back again to the original state (a noninverted state) on the first falling edge of TCK after leaving the Run-Test/Idle TAP Controller state. 15.5.7 EXTEST TRAIN This IEEE 1149.6 instruction applies only to the AC-coupled pins. All DC pins will perform as if the IEEE Std 1149.1 EXTEST instruction is operating whenever the EXTEST_PULSE instruction is effective. The EXTEST_TRAIN instruction enables edge-detecting behavior on signal paths containing AC pins, where test receivers reconstruct the original waveform created by a driver even when signals decay due to AC-coupling. As the operation name suggests, enabling EXTEST_TRAIN causes a pulse train to be issued which can be detected even on AC-coupled receivers. Once in an enabled state, the train will be sent continuously in response to the TCK clock. No other signaling is required to generate the pulse train while in this state. Refer to the IEEE Std 1149.6 for full details. Below is a short synopsis. First, the output signal is forced to the state matching the value (a non-inverted state) in its associated Boundary-Scan Register data cell for its driver (true and inverted values for a differential pair), at the falling edge of TCK in update-IR. Then the output signal transitions to the opposite state (an inverted state) on the first falling edge of TCK that occurs after entering the Run-Test/Idle TAP Controller state. While remaining in this state, the output signal will continue to invert on every falling edge of TCK, thereby generating a pulse train. 15.5.8 RESERVED Reserved instructions implement various test modes used in the device manufacturing process. The user should not enable these instructions. 15.5.9 PRIVATE Private instructions implement various test modes used in the device manufacturing process. The user should not enable these instructions.
15.6 Usage Considerations
As previously stated, there are internal pull-ups on TRST, TMS, and TDI. However, TCK also needs to be driven to a known value. It is best to either drive a zero on the TCK pin when it is not being used or to use an external pull-down resistor. In order to guarantee that the JTAG does not interfere with normal system operation, the TAP controller should be forced into the Test-Logic-Reset controller state by continuously holding TRST low and/or TMS high when the chip is in normal operation. If JTAG will not be used, externally pull-down TRST low to disable it.
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IDT 80KSBR200
Advanced Datasheet*
Notes
15.7 JTAG Configuration Register Access
As previously mentioned, the JTAG port may be used to read and write to the 80KSBR200's configuration registers. The same JTAG instruction (4b1010) is used for both writes and reads.
Bits
0 [22:1]
Field Name
jtag_config_wr_n jtag_config_addr 1 22
Size
Description
1 - read configuration register 0 - write configuration register Starting address of the memory mapped configuration register. 22 address bits map to a unique double-word aligned on a 32-bit boundary. This provides accessibility to and is consistent with the sRIO memory mapping. Reads: Data shifted out (one 32-bit word per read) is read from the configuration register at address jtag_config_addr. Writes: Data shifted in (one 32-bit word per write) is written to the configuration register at address jtag_config_addr.
[54:23]
jtag_config_data
32
Table 107 Data Stream for JTAG Configuration Register Access Mode
15.7.1 Writes during Configuration Register Access A write is performed by shifting the CRA OPcode into the Instruction Register (IR), then shifting in first a read / write select bit, then both the 22-bit target address and 32-bit data into the Data Register (DR). When bit 0 of the data stream is 0, data shifted in after the address will be written to the address specified in jtag_config_addr. The TDO pin will transmit all 0s. See the figure below for the associated timing diagram.
Figure 47 Implementation of write during configuration register access
15.7.2 Reads during Configuration Register Access Reads are much like writes except that target data is not provided. When bit 0 of the data stream is 1, data shifted out will be read from the address specified in jtag_config_addr. TDI will not be used after the address is shifted in. As a function of read latency in the architecture, the first 16 bits will be 0's and must be ignored. The following bits will contain the actual register bits.
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IDT 80KSBR200
Advanced Datasheet*
Notes
Figure 48 Implementation of read during configuration register access
15.8 JTAG DC Electrical Specifications
At recommended operating conditions with VDD3 = 3.3V 5%
Figure 49 JTAG DC Electrical Specifications (VDD3 = 3.3V 5%)
At recommended operating conditions with VDD3 = 2.5V 100mV
Figure 50 JTAG DC Electrial Specifications (VDD3 = 2.5V 100mV )
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IDT 80KSBR200
Advanced Datasheet*
Notes
15.9 JTAG AC Electrical Specifications
80KSBR200 Symbol tJCYC tJCH tJCL tJR tJF tJRST tJRSR tJCD tJDC tJS tJH Parameter JTAG Clock Input Period JTAG Clock HIGH JTAG Clock Low JTAG Clock Rise Time JTAG Clock Fall Time JTAG Reset JTAG Reset Recovery JTAG Data Output JTAG Data Output Hold JTAG Setup JTAG Hold Min. 100 40 40
____
Max.
____
Units ns ns ns ns ns ns ns ns ns ns ns
5686 tbl 02
____
____
3
(1)
____
3(1)
____
50 50
____
____
25
____
0 15 15
____
____
Figure 51 JTAG AC Electrical Specifications
Note: 1. 2. 3. 4. Guaranteed by design. 30pF loading on external output signals. Refer to AC Electrical Test Conditions stated earlier in this document. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
15.10 JTAG Timing Specification
Range Symbol Parameter Min. Max. Unit Notes Voltage relative to COMMON of either signal comprising a differential pair
VO
Output Voltage
-0.40
2.30
Volts
VDIFF JD JT
PP
Differential Output Voltage Deterministic Jitter Total Jitter Multiple Output Skew Unit Interval
800
____
1600 0.17 0.35 1000 320
mV p-p UI p-p UI p-p ps ps Skew at the transmitter output between lanes of a multilane link +/- 100 ppm
5686 tbl 08
____
SMO UI
____
320
Figure 52 JTAG Timing Specifications
Note: 1. 2. Device inputs = All device inputs except TDI, TMS, and TRST. Device outputs = All device outputs except TDO.
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IDT 80KSBR200
Advanced Datasheet*
16.0 Pinout & Pin Listing
16.1 Pinout
Figure 53 80KSBR200 Pinout
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IDT 80KSBR200
Advanced Datasheet*
16.2 Pin Listing
Table 108 Pin Listing (Alphabetical)
Pin Number V17
Pin Name A0
Function QDR ADDR 0
Supply / Interface (VDDQ, GND) / CMOS Output
Pin Function Description When operating as a FIFO controller, the A output is the address for the external memory and should be connected directly to the SA lines on the QDRII B4 SRAM. When operating as a FIFO controller, the A output is the address for the external memory and should be connected directly to the SA lines on the QDRII B4 SRAM. When operating as a FIFO controller, the A output is the address for the external memory and should be connected directly to the SA lines on the QDRII B4 SRAM. When operating as a FIFO controller, the A output is the address for the external memory and should be connected directly to the SA lines on the QDRII B4 SRAM. When operating as a FIFO controller, the A output is the address for the external memory and should be connected directly to the SA lines on the QDRII B4 SRAM. When operating as a FIFO controller, the A output is the address for the external memory and should be connected directly to the SA lines on the QDRII B4 SRAM. When operating as a FIFO controller, the A output is the address for the external memory and should be connected directly to the SA lines on the QDRII B4 SRAM. When operating as a FIFO controller, the A output is the address for the external memory and should be connected directly to the SA lines on the QDRII B4 SRAM. When operating as a FIFO controller, the A output is the address for the external memory and should be connected directly to the SA lines on the QDRII B4 SRAM. When operating as a FIFO controller, the A output is the address for the external memory and should be connected directly to the SA lines on the QDRII B4 SRAM. When operating as a FIFO controller, the A output is the address for the external memory and should be connected directly to the SA lines on the QDRII B4 SRAM. When operating as a FIFO controller, the A output is the address for the external memory and should be connected directly to the SA lines on the QDRII B4 SRAM. When operating as a FIFO controller, the A output is the address for the external memory and should be connected directly to the SA lines on the QDRII B4 SRAM. When operating as a FIFO controller, the A output is the address for the external memory and should be connected directly to the SA lines on the QDRII B4 SRAM.
AB19
A1
QDR ADDR 1
(VDDQ, GND) / CMOS Output
W17
A2
QDR ADDR 2
(VDDQ, GND) / CMOS Output
AB20
A3
QDR ADDR 3
(VDDQ, GND) / CMOS Output
AA18
A4
QDR ADDR 4
(VDDQ, GND) / CMOS Output
AA20
A5
QDR ADDR 5
(VDDQ, GND) / CMOS Output
Y18
A6
QDR ADDR 6
(VDDQ, GND) / CMOS Output
AA21
A7
QDR ADDR 7
(VDDQ, GND) / CMOS Output
W18
A8
QDR ADDR 8
(VDDQ, GND) / CMOS Output
Y20
A9
QDR ADDR 9
(VDDQ, GND) / CMOS Output
W19
A10
QDR ADDR 10
(VDDQ, GND) / CMOS Output
Y21
A11
QDR ADDR 11
(VDDQ, GND) / CMOS Output
V19
A12
QDR ADDR 12
(VDDQ, GND) / CMOS Output
AA22
A13
QDR ADDR 13
(VDDQ, GND) / CMOS Output
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IDT 80KSBR200 AA19 A14 QDR ADDR 14 (VDDQ, GND) / CMOS Output
Advanced Datasheet* When operating as a FIFO controller, the A output is the address for the external memory and should be connected directly to the SA lines on the QDRII B4 SRAM. When operating as a FIFO controller, the A output is the address for the external memory and should be connected directly to the SA lines on the QDRII B4 SRAM. When operating as a FIFO controller, the A output is the address for the external memory and should be connected directly to the SA lines on the QDRII B4 SRAM. When operating as a FIFO controller, the A output is the address for the external memory and should be connected directly to the SA lines on the QDRII B4 SRAM. When operating as a FIFO controller, the A output is the address for the external memory and should be connected directly to the SA lines on the QDRII B4 SRAM. When operating as a FIFO controller, the A output is the address for the external memory and should be connected directly to the SA lines on the QDRII B4 SRAM. When operating as a FIFO controller, the A output is the address for the external memory and should be connected directly to the SA lines on the QDRII B4 SRAM. I2C address width select. Set ADS = GND for 7-bit SerB slave address. ADS = Vdd for 10-bit. NOTE: SUPPLY / LEVELS REQUIREMENTS ARE UNQUE FROM THE OTHER I2C PINS. Auxiliary clocks provided to bypass CDR block for DC-type testing of SERDES RX inputs. Auxiliary clocks provided to bypass CDR block for DC-type testing of SERDES RX inputs. (VDD, GND) / CMOS Input Clock input for the P-Port. These inputs should be connected to the CQ/nCQ outputs of the QDR SRAM when operating as a FIFO controller. Clock input for the P-Port. These inputs should be connected to the CQ/nCQ outputs of the QDR SRAM when operating as a FIFO controller. Clock output that is closely aligned with parallel port data output (Q), address (A), Queue Empty (E), and Queue Full (F). When operating as a FIFO controller, outputs read (nRd), and write (nWr) are also aligned. The alignment is selectable as either center aligned or edge aligned in the configuration register. When PPM is LOW, this output should be connected to the K and nK inputs of the QDR SRAM. Clock output that is closely aligned with parallel port data output (Q), address (A), Queue Empty (E), and Queue Full (F). When operating as a FIFO controller, outputs read (nRd), and write (nWr) are also aligned. The alignment is selectable as either center aligned or edge aligned in the configuration register. When PPM is LOW, this output should be connected to the K and nK inputs of the QDR SRAM.
Y22
A15
QDR ADDR 15
(VDDQ, GND) / CMOS Output
V21
A16
QDR ADDR 16
(VDDQ, GND) / CMOS Output
W22
A17
QDR ADDR 17
(VDDQ, GND) / CMOS Output
V18
A18
QDR ADDR 18
(VDDQ, GND) / CMOS Output
V22
A19
QDR ADDR 19
(VDDQ, GND) / CMOS Output
U18
A20
QDR ADDR 20
(VDDQ, GND) / CMOS Output
C6
ADS
I2C
(VDD, GND) / CMOS Input
U3 V3 E21
AUXCKI AUXCKQ CKI
AUX ClockI AUX ClockQ P-Port Clock
E22
CKI_N
P-Port Clock
(VDD, GND) / CMOS Input
H18
CKO
Echo Clock
(VDD, GND) / CMOS Output
G18
CKO_N
Echo Clock
(VDD, GND) / CMOS Output
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IDT 80KSBR200 C13 A16 D14 F20 B16 C14 D22 A17 B14 D21 E15 B22 B17 D15 C21 A18 C15 E19 C17 B15 D20 D17 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 QDR SRAM Data In 0 QDR SRAM Data In 1 QDR SRAM Data In 2 QDR SRAM Data In 3 QDR SRAM Data In 4 QDR SRAM Data In 5 QDR SRAM Data In 6 QDR SRAM Data In 7 QDR SRAM Data In 8 QDR SRAM Data In 9 QDR SRAM Data In 10 QDR SRAM Data In 11 QDR SRAM Data In 12 QDR SRAM Data In 13 QDR SRAM Data In 14 QDR SRAM Data In 15 QDR SRAM Data In 16 QDR SRAM Data In 17 QDR SRAM Data In 18 QDR SRAM Data In 19 QDR SRAM Data In 20 QDR SRAM Data In 21 (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input The QDR Input Data Bus 0 The QDR Input Data Bus 1 The QDR Input Data Bus 2 The QDR Input Data Bus 3 The QDR Input Data Bus 4 The QDR Input Data Bus 5 The QDR Input Data Bus 6 The QDR Input Data Bus 7 The QDR Input Data Bus 8 The QDR Input Data Bus 9 The QDR Input Data Bus 10 The QDR Input Data Bus 11 The QDR Input Data Bus 12 The QDR Input Data Bus 13 The QDR Input Data Bus 14 The QDR Input Data Bus 15 The QDR Input Data Bus 16 The QDR Input Data Bus 17 The QDR Input Data Bus 18 The QDR Input Data Bus 19 The QDR Input Data Bus 20 The QDR Input Data Bus 21
Advanced Datasheet*
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IDT 80KSBR200 A15 B21 B18 D16 B20 A19 E16 D19 D18 E17 C19 B19 E18 A20 A1 A8 A9 A10 A22 B2 B8 B9 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 GND GND GND GND GND GND GND GND QDR SRAM Data In 22 QDR SRAM Data In 23 QDR SRAM Data In 24 QDR SRAM Data In 25 QDR SRAM Data In 26 QDR SRAM Data In 27 QDR SRAM Data In 28 QDR SRAM Data In 29 QDR SRAM Data In 30 QDR SRAM Data In 31 QDR SRAM Data In 32 QDR SRAM Data In 33 QDR SRAM Data In 34 QDR SRAM Data In 35 Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input (VDDQ, GND) / CMOS Input The QDR Input Data Bus 22 The QDR Input Data Bus 23 The QDR Input Data Bus 24 The QDR Input Data Bus 25 The QDR Input Data Bus 26 The QDR Input Data Bus 27 The QDR Input Data Bus 28 The QDR Input Data Bus 29 The QDR Input Data Bus 30 The QDR Input Data Bus 31 The QDR Input Data Bus 32 The QDR Input Data Bus 33 The QDR Input Data Bus 34 The QDR Input Data Bus 35
Advanced Datasheet*
Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane.
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IDT 80KSBR200 C1 C3 C18 D1 D3 D10 D12 E7 E9 E11 E13 F6 F8 F10 F12 F14 F16 F19 F21 G7 G9 G11 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS)
Advanced Datasheet* Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane.
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200 G13 G15 G17 H6 H8 H10 H12 H14 H16 H20 J7 J9 J11 J13 J15 J17 K6 K8 K10 K12 K14 K16 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS)
Advanced Datasheet* Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane.
151 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200 K20 L7 L9 L11 L13 L15 L17 M6 M8 M10 M12 M14 M16 M20 N7 N9 N11 N13 N15 N17 P6 P8 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS)
Advanced Datasheet* Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane.
152 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200 P10 P12 P14 P16 P20 R7 R9 R11 R13 R15 R17 T6 T8 T10 T12 T14 T16 T20 U5 U7 U9 U11 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS)
Advanced Datasheet* Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane.
153 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200 U13 U15 U17 V20 W1 Y19 AB1 AB2 AB16 AB22 G1 G3 H2 M2 N1 N3 Y7 Y13 AA8 AA12 AB7 AB13 GND GND GND GND GND GND GND GND GND GND GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Digital Ground (CMOS) Analog Ground (CMOS) Analog Ground (CMOS) Analog Ground (CMOS) Analog Ground (CMOS) Analog Ground (CMOS) Analog Ground (CMOS) Analog Ground (CMOS) Analog Ground (CMOS) Analog Ground (CMOS) Analog Ground (CMOS) Analog Ground (CMOS) Analog Ground (CMOS)
Advanced Datasheet* Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Digital GND. All pins must be tied to single potential ground plane. Analog GND. All pins must be tied to single potential ground plane. Analog GND. All pins must be tied to single potential ground plane. Analog GND. All pins must be tied to single potential ground plane. Analog GND. All pins must be tied to single potential ground plane. Analog GND. All pins must be tied to single potential ground plane. Analog GND. All pins must be tied to single potential ground plane. Analog GND. All pins must be tied to single potential ground plane. Analog GND. All pins must be tied to single potential ground plane. Analog GND. All pins must be tied to single potential ground plane. Analog GND. All pins must be tied to single potential ground plane. Analog GND. All pins must be tied to single potential ground plane. Analog GND. All pins must be tied to single potential ground plane.
154 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200 C7 GNDS SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS)
Advanced Datasheet* Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane.
C9
GNDS
D5
GNDS
E2
GNDS
E4
GNDS
F5
GNDS
H4
GNDS
H5
GNDS
K2
GNDS
K4
GNDS
K5
GNDS
M4
GNDS
M5
GNDS
P5
GNDS
R2
GNDS
R4
GNDS
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March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200 T1 GNDS SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS)
Advanced Datasheet* Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane.
T3
GNDS
T5
GNDS
V2
GNDS
V4
GNDS
V6
GNDS
V8
GNDS
V10
GNDS
V12
GNDS
V14
GNDS
V16
GNDS
W2
GNDS
W5
GNDS
W8
GNDS
W10
GNDS
W12
GNDS
156 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200 W15 GNDS SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) SERDES Ground (CMOS) I2C (VDD, GND) / CMOS Input
Advanced Datasheet* Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. Analog GND for TX/RX pairs. All pins must be tied to single potential ground plane. I2C Slave ID address bit 0. This should be set statically to Vdd or GND at power-up. NOTE: SUPPLY / LEVELS REQUIREMENTS ARE UNQUE FROM THE OTHER I2C PINS. I2C Slave ID address bit 1. This should be set statically to Vdd or GND at power-up. I2C Slave ID address bit 2. This should be set statically to Vdd or GND at power-up. I2C Slave ID address bit 3. This should be set statically to Vdd or GND at power-up. I2C Slave ID address bit 4. This should be set statically to Vdd or GND at power-up. I2C Slave ID address bit 5. This should be set statically to Vdd or GND at power-up. I2C Slave ID address bit 6. This should be set statically to Vdd or GND at power-up. I2C Slave ID address bit 8. This should be set statically to Vdd or GND at power-up. I2C Slave ID address bit 7. This should be set statically to Vdd or GND at power-up. I2C Slave ID address bit 9. This should be set statically to Vdd or GND at power-up. sRIO 8/16 bit Destination ID Select This is an interrupt output pin whose value is given by the Error Management Block.
Y4
GNDS
Y16
GNDS
AA5
GNDS
AA10
GNDS
AA15
GNDS
AB4
GNDS
A6
ID0
B6 A7 B7 D6 C8 D8 C10 C11 C12 U2 AA1
ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 IDS IRQ0
I2C I2C I2C I2C I2C I2C I2C I2C I2C ID Select Interrupt 0
(VDD, GND) / CMOS Input (VDD, GND) / CMOS Input (VDD, GND) / CMOS Input (VDD, GND) / CMOS Input (VDD, GND) / CMOS Input (VDD, GND) / CMOS Input (VDD, GND) / CMOS Input (VDD, GND) / CMOS Input (VDD, GND) / CMOS Input (VDD, GND) / CMOS Input (VDD3, GND) / CMOS Output
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200 Y1 A11 B11 B3 IRQ1 MBDONE MBPASS MRST_N Interrupt 1 Memory BIST Memory BIST Master Reset (VDD3, GND) / CMOS Output (VDD, GND) / CMOS Output (VDD, GND) / CMOS Output (VDD, GND) / CMOS Input
Advanced Datasheet* This is an interrupt output pin whose value is given by the Error Management Block. MBIST Done. Set (MBDONE = 1) when MBIST patterns are completed MBIST Pass. Set (MBPASS = 1) when MBIST patterns pass. Cleared (MBPASS = 0) and is sticky when MBIST fails. SerB Global Reset. Sets all internal registers to default values. Resets all PLLs. Resets all port configurations. This is a HARD Reset. Used for device testing with PLL bypass. PPE = 0, P-Port is active PPE = 1, P-Port is powered down and not used (low power). The QDR Output Data Bus 0 The QDR Output Data Bus 1 The QDR Output Data Bus 2 The QDR Output Data Bus 3 The QDR Output Data Bus 4 The QDR Output Data Bus 5 The QDR Output Data Bus 6 The QDR Output Data Bus 7 The QDR Output Data Bus 8 The QDR Output Data Bus 9 The QDR Output Data Bus 10 The QDR Output Data Bus 11 The QDR Output Data Bus 12 The QDR Output Data Bus 13 The QDR Output Data Bus 14 The QDR Output Data Bus 15
Y17 B10 P18 R18 P19 R19 T21 U21 T22 U22 N19 N18 R22 R21 P22 P21 N22 N21
PLL_OFF PPE_N Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15
PLL Off Parallel Port Enable QDR SRAM Data Out 0 QDR SRAM Data Out 1 QDR SRAM Data Out 2 QDR SRAM Data Out 3 QDR SRAM Data Out 4 QDR SRAM Data Out 5 QDR SRAM Data Out 6 QDR SRAM Data Out 7 QDR SRAM Data Out 8 QDR SRAM Data Out 9 QDR SRAM Data Out 10 QDR SRAM Data Out 11 QDR SRAM Data Out 12 QDR SRAM Data Out 13 QDR SRAM Data Out 14 QDR SRAM Data Out 15
(VDD, GND) / CMOS Input (VDD, GND) / CMOS Input (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output
158 of 172
March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200 M22 M21 L21 L22 K21 K22 J21 J22 L18 L19 H21 H22 G21 G22 K18 K19 H19 J19 J18 G19 AA17 AB18 Q16 Q17 Q18 Q19 Q20 Q21 Q22 Q23 Q24 Q25 Q26 Q27 Q28 Q29 Q30 Q31 Q32 Q33 Q34 Q35 QDRA QDRB QDR SRAM Data Out 16 QDR SRAM Data Out 17 QDR SRAM Data Out 18 QDR SRAM Data Out 19 QDR SRAMData Out 20 QDR SRAM Data Out 21 QDR SRAM Data Out 22 QDR SRAM Data Out 23 QDRSRAM Data Out 24 QDR SRAM Data Out 25 QDR SRAM Data Out 26 QDR SRAM Data Out 27 QDR SRAM Data Out 28 QDR SRAM Data Out 29 QDR SRAM Data Out 30 QDR SRAM Data Out 31 QDR SRAM Data Out 32 QDR SRAM Data Out 33 QDR SRAM Data Out 34 QDR SRAM Data Out 35 QDR Mem Size QDR Mem Size (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDDQ, GND) / CMOS Output (VDD, GND) / CMOS Input (VDD, GND) / CMOS Input The QDR Output Data Bus 16 The QDR Output Data Bus 17 The QDR Output Data Bus 18 The QDR Output Data Bus 19 The QDR Output Data Bus 20 The QDR Output Data Bus 21 The QDR Output Data Bus 22 The QDR Output Data Bus 23 The QDR Output Data Bus 24 The QDR Output Data Bus 25 The QDR Output Data Bus 26 The QDR Output Data Bus 27 The QDR Output Data Bus 28 The QDR Output Data Bus 29 The QDR Output Data Bus 30 The QDR Output Data Bus 31 The QDR Output Data Bus 32 The QDR Output Data Bus 33 The QDR Output Data Bus 34 The QDR Output Data Bus 35
Advanced Datasheet*
Reserved and should be tied to Ground. Specifies what size QDR SRAM is connected externally. 0 = 16 address lines are active (36M QDR2 B4 SRAM) 1 = 17 address lines are active (72M QDR2 B4 SRAM)
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200 V21 RDO_N Read Strobe (VDD, GND) / CMOS Output
Advanced Datasheet* When QDR type SRAM attached, this output should be connected to the /Rd input on the QDR SRAM(s). The FIFO controller will use this pin to control the read function on the SRAM. Negative side of differential input clock. This clock is used as the 156MHz reference for standard SERDES operation. Positive side of differential input clock. This clock is used as the 156MHz reference for standard SERDES operation. External bias resistor. This pin must be connected to Rextp with a 12k Ohm resistor. This establishes the drive bias on the SERDES output. This provides CML driver stability across process and temperature. External bias resistor. This pin must be connected to Rextn with a 12k Ohm resistor. (VDDS, GNDS) / S-Port 1 Differential Input (VDDS, GNDS) / S-Port 1 Differential Input (VDDS, GNDS) / S-Port 1 Differential Input (VDDS, GNDS) / S-Port 1 Differential Input (VDDS, GNDS) / S-Port 1 Differential Input (VDDS, GNDS) / S-Port 1 Differential Input (VDDS, GNDS) / S-Port 1 Differential Input (VDDS, GNDS) / S-Port 1 Differential Input (VDDS, GNDS) / S-Port 1 Differential Output (VDDS, GNDS) / S-Port 1 Differential Output (VDDS, GNDS) / S-Port 1 Differential Output (VDDS, GNDS) / S-Port 1 Differential Output (VDDS, GNDS) / S-Port 1 Differential Output (VDDS, GNDS) / S-Port 1 Differential Output (VDDS, GNDS) / S-Port 1 Differential Output (VDDS, GNDS) / RIO Differential Output Negative end of differential receiver, S-Port, Lane 0 Positive end of differential receiver, S-Port, Lane 0 Negative end of differential receiver, S-Port, Lane 1 Positive end of differential receiver, S-Port, Lane 1 Negative end of differential receiver, S-Port, Lane 2 Positive end of differential receiver, S-Port, Lane 2 Negative end of differential receiver, S-Port, Lane 3 Positive end of differential receiver, S-Port, Lane 3 Negative end of differential transmitter, S-Port, Lane 0 Positive end of differential transmitter, S-Port, Lane 0 Negative end of differential transmitter, S-Port, Lane 1 Positive end of differential transmitter, S-Port, Lane 1 Negative end of differential transmitter, S-Port, Lane 2 Positive end of differential transmitter, S-Port, Lane 2 Negative end of differential transmitter, S-Port, Lane 3 Positive end of differential transmitter, S-Port, Lane 3
AB3 AA3 V1
REFCLKN REFCLKP REXTN
SERDES Clock SERDES Clock Rext
(VDD, GND) / Differential Input (VDD, GND) / Differential Input
U1 L1 M1 L4 L3 J1 H1 J4 J3 P1 P2 P4 N4 F1 F2 F4 G4
REXTP S1_RXN0 S1_RXP0 S1_RXN1 S1_RXP1 S1_RXN2 S1_RXP2 S1_RXN3 S1_RXP3 S1_TXN0 S1_TXP0 S1_TXN1 S1_TXP1 S1_TXN2 S1_TXP2 S1_TXN3 S1_TXP3
Rext Port 1 Receive Port 1 Receive Port 1 Receive Port 1 Receive Port 1 Receive Port 1 Receive Port 1 Receive Port 1 Receive Port1 Transmit Port1 Transmit Port1 Transmit Port1 Transmit Port1 Transmit Port1 Transmit Port1 Transmit Port1 Transmit
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200 AB6 AA6 W6 W7 AB14 AA14 W14 W13 AB9 AB8 W9 Y9 AB11 AB12 W11 Y11 B12 S2_RXN0 S2_RXP0 S2_RXN1 S2_RXP1 S2_RXN2 S2_RXP2 S2_RXN3 S2_RXP3 S2_TXN0 S2_TXP0 S2_TXN1 S2_TXP1 S2_TXN2 S2_TXP2 S2_TXN3 S2_TXP3 SCEN Port 2 Receive Port 2 Receive Port 2 Receive Port 2 Receive Port 2 Receive Port 2 Receive Port 2 Receive Port 2 Receive Port 2 Transmit Port 2 Transmit Port 2 Transmit Port 2 Transmit Port 2 Transmit Port 2 Transmit Port 2 Transmit Port 2 Transmit SCAN (VDDS, GNDS) (VDDS, GNDS) (VDDS, GNDS) (VDDS, GNDS) (VDDS, GNDS) (VDDS, GNDS) (VDDS, GNDS) (VDDS, GNDS) (VDDS, GNDS) (VDDS, GNDS) (VDDS, GNDS) (VDDS, GNDS) (VDDS, GNDS) (VDDS, GNDS) (VDDS, GNDS) (VDDS, GNDS) (VDD, GND) / CMOS Input
Advanced Datasheet* Negative end of differential receiver, S-Port 2, Lane 0 Positive end of differential receiver, S-Port 2, Lane 0 Negative end of differential receiver, S-Port 2, Lane 1 Positive end of differential receiver, S-Port 2, Lane 1 Negative end of differential receiver, S-Port 2, Lane 2 Positive end of differential receiver, S-Port 2, Lane 2 Negative end of differential receiver, S-Port 2, Lane 3 Positive end of differential receiver, S-Port 2, Lane 3 Negative end of differential transmitter, S-Port 2, Lane 0 Positive end of differential transmitter, S-Port 2, Lane 0 Negative end of differential transmitter, S-Port 2, Lane 1 Positive end of differential transmitter, S-Port 2, Lane 1 Negative end of differential transmitter, S-Port 2, Lane 2 Positive end of differential transmitter, S-Port 2, Lane 2 Negative end of differential transmitter, S-Port 2, Lane 3 Positive end of differential transmitter, S-Port 2, Lane 3 SCAN Enable. SCAN is enabled when SCEN = 1. Scan clock is provided by SCK while SCEN = 1. Internal pull-down ensures disable if this pin is not driven. I2C Clock. This is also repurposed for the SCAN clock when SCEN = 1. I2C Serial Data IO. Data direction is determined by the I2C Read/ Write bit. See I2C functionality for further detail. Speed Select Pins. These pins define S-Port port speed at RESET for all ports. The RESET setting may be overridden by subsequent programming of the QUAD_CTRL register. SP1S[1:0] = {00 = 1.25G, 01 = 2.5G, 10 = 3.125G, 11 = RESERVED}. These pins must remain STATICALLY BIASED after power-up. Speed Select Pins. These pins define S-Port port speed at RESET for all ports. SERDES Analog Test Output. Used for observing SERDES outputs. SERDES Digital Test Output. Used for observing SERDES outputs. (VDD3, GND) / CMOS Input (VDD3, GND) / CMOS Input (VDD3, GND) / CMOS Output JTAG Tap Port Clock JTAG Tap Port Input JTAG Tap Port Output
C4 C5 W3
SCL SDA SP1S0
I2C I2C S-Port 1 Speed Select
(VDD3, GND) / CMOS Input (VDD3, GND) / CMOS IO (VDD, GND) / CMOS Input
Y3 AA2 Y2 B4 B5 A5
SP1S1 STOA STOD TCK TDI TDO
S-Port 1 Speed Select SERDES Analog SERDES Digital JTAG JTAG JTAG
(VDD, GND) / CMOS Input
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200 A14 TM0 TMODE0 (VDD3, GND) / CMOS Input
Advanced Datasheet* TM[2:0]; MBIST Enable for use in testing on-chip memories. MBIST is enabled when mben = 1. Internal pull-down ensures disable if this pin is not driven. TM[2:0]; MBIST Enable for use in testing on-chip memories. TM[2:0]; MBIST Enable for use in testing on-chip memories. JTAG Tap Port Mode Select JTAG Tap Port Asynchronous Reset Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane.
B13 A12 A3 A4 C22 D2 D4 D11 D13 E6 E8 E10 E12 E14 E20 F7 F9 F11 F13 F17 G6 G8
TM1 TM2 TMS TRST VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
TMODE1 TMODE2 JTAG JTAG 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS)
(VDD3, GND) / CMOS Input (VDD3, GND) / CMOS Input (VDD3, GND) / CMOS Input (VDD3, GND) / CMOS Input
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200 G10 G12 G14 H7 H9 H11 H13 J6 J8 J10 J12 J14 K7 K9 K11 K13 L6 L8 L10 L12 L14 M7 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS)
Advanced Datasheet* Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane.
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200 M9 M11 M13 N6 N8 N10 N12 N14 P7 P9 P11 P13 R6 R8 R10 R12 R14 T7 T9 T11 T13 U4 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS)
Advanced Datasheet* Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane.
164 of 172
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200 U6 U8 U10 U12 U14 A2 VDD VDD VDD VDD VDD VDD3 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 1.2V Digital Power (CMOS) 2.5V / 3.3V JTAG Power (CMOS) 2.5V / 3.3V JTAG Power (CMOS) 2.5V / 3.3V JTAG Power (CMOS) Analog Power (CMOS) Analog Power (CMOS) Analog Power (CMOS) Analog Power (CMOS) Analog Power (CMOS) Analog Power (CMOS) Analog Power (CMOS) Analog Power (CMOS) Analog Power (CMOS) Analog Power (CMOS) Analog Power (CMOS) Analog Power (CMOS) 1.5V Digital Power (CMOS)
Advanced Datasheet* Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital JTAG Pin VDD3. All pins must be tied to single potential power supply plane. Digital JTAG Pin VDD3. All pins must be tied to single potential power supply plane. Digital JTAG Pin VDD3. All pins must be tied to single potential power supply plane. Analog VDD. All pins must be tied to single potential power supply plane. Analog VDD. All pins must be tied to single potential power supply plane. Analog VDD. All pins must be tied to single potential power supply plane. Analog VDD. All pins must be tied to single potential power supply plane. Analog VDD. All pins must be tied to single potential power supply plane. Analog VDD. All pins must be tied to single potential power supply plane. Analog VDD. All pins must be tied to single potential power supply plane. Analog VDD. All pins must be tied to single potential power supply plane. Analog VDD. All pins must be tied to single potential power supply plane. Analog VDD. All pins must be tied to single potential power supply plane. Analog VDD. All pins must be tied to single potential power supply plane. Analog VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane.
B1
VDD3
C2
VDD3
F3 G2 H3 M3 N2 P3 Y6 Y8 Y12 Y14 AA7 AA13 A21
VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDA VDDQ
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IDT 80KSBR200 C16 C20 F15 F18 F22 G16 G20 H15 H17 J16 J20 K15 K17 L16 L20 M15 M17 N16 N20 P15 P17 R16 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS)
Advanced Datasheet* Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane.
166 of 172
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200 R20 T15 T17 U16 U20 W20 AB21 D7 D9 E1 E3 E5 G5 J2 J5 K1 K3 L2 L5 N5 R1 R3 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) 1.5V Digital Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS)
Advanced Datasheet* Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Digital VDD. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane.
167 of 172
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200 R5 T2 T4 V5 V7 V9 V11 V13 V15 W4 W16 Y5 Y10 Y15 AA4 AA9 AA11 AA16 AB5 AB10 AB15 A13 VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VDDS VREF SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) SERDES Power (CMOS) Reference Voltage (CMOS)
Advanced Datasheet* Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Analog VDD for TX/RX pairs. All pins must be tied to single potential power supply plane. Toggle point reference voltage for HSTL inputs
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200 U19 WRO_N Write Strobe (VDD, GND) / CMOS Output
Advanced Datasheet* When QDR type SRAM attached, this output should be connected to the /Wr input on the QDR SRAM(s). The FIFO controller will use this pin to control the write function on the SRAM.
AB17 M18 M19 T18 T19
ZQ DNC DNC DNC DNC
P-Port Impedance Do Not Connect Do Not Connect Do Not Connect Do Not Connect
17.0 Package Specifications
17.1 Package Physical & Thermal Specifications
Package: Super FlipChip FCBGA(BR484) Dimensions: 23 x 23mm Ball Count: 484 Ball Diameter: 0.6mm Ball Pitch: 1.0mm Theta JA = {11.9C/W @ 0m/s, 8 C/W @ 1m/s, 7.3 C/W @ 2m/s} Theta JC = 0.2 C/W
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
17.2 Package Drawing
IDT
Figure 54 SerB Package Drawing 1 of 2 170 of 172
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March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
IDT
Figure 55 SerB Package Drawing 2 of 2 171 of 172
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March 19, 2007
2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
18.0 References and Standards
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [14] "The I2C-Bus Specification", version 2.1, January 2000, Phillips RapidIOTM Interconnect Specification, Part 1: Input/Output Logical Specification, Rev. 1.3, 06/2005, RTA RapidIOTM Interconnect Specification, Part 2: Message Passing Logical Specification, Rev. 1.3, 06/2005, RTA RapidIOTM Interconnect Specification, Part 3: Common Transport Specification, Rev. 1.3, 06/2005, RTA RapidIOTM Interconnect Specification, Part 6: 1x/4x LP-Serial Physical Layer Specification, Rev. 1.3, 06/2005, RTA RapidIOTM Interconnect Specification, Part 7: System and Device Inter-operability Specification, Rev. 1.3, 06/2005, RTA RapidIOTM Interconnect Specification, Part 8: Error Management Extensions Specification, Rev. 1.3, 06/2005, RTA RapidIOTM Interconnect Specification, Part 9: Flow Control Logic Layer Extensions Specification, Rev. 1.3, 06/2005, RTA RapidIOTM Interconnect Specification, Annex I: Software/System Bring Up Specification, Rev. 1.3, 06/2005, RTA RapidIOTM Specification Revision 1.2: Errata 1, Rev. 1, 06/2003, RapidIOTM Trade Association IEEE Std 1149.1-2001 IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Std 1149.6-2003 IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks JEDEC Standard, JESD8-6 HSTL
[13] QDR2 SRAM, Datasheet, Samsung, K7R163684B
19.0 Revision History
10/06/06: Initial Advanced Datasheet (Rev A) 03/01/07: Advanced Datasheet (Rev B)
19.1 Advanced Datasheet: (Definition)
"ADVANCED datasheet contain descriptions for products that are in early release. "Advanced datasheets are informational only. Advanced specifications are subject to change without notice.
20.0 Ordering Information
For specific speeds, packages and powers, contact your sales office
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2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.

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